Appendix D: Mounting Precautions
AP-42
Seiko Epson Corporation
S1C17601 TECHNICAL MANUAL
Noise-induced malfunctions
Check the following three points if you suspect the presence of noise-induced IC malfunctions.
(1) DSIO pin
Low-level noise to this pin will cause a switch to Debug mode. The switch to Debug mode can be
confirmed by the clock output from DCLK and a High signal from the DST2 pin.
For the product version, we recommend connecting the DSIO pin directly to HVDD or pulling up the DISO
pin using a resistor not exceeding 10 k
.
The IC includes an internal pull-up resistor. The resistor has a relatively high impedance of 100 k
to 500
k
and is not noise-resistant.
(2) #RESET pin
Low-level noise to this pin will reset the IC. Depending on the input waveform, the reset may not proceed
correctly.
This is more likely to occur if, due to circuit design choices, the impedance is high when the reset input is High.
(3) VDD and VSS power supply
The IC will malfunction the instant noise falling below the rated voltage is input.
Incorporate countermeasures on the circuit board, including close patterns for circuit board power supply
circuits, noise-filtering decoupling capacitors, and surge/noise prevention components on the power supply
line.
Perform the inspections described above using an oscilloscope capable of observing waveforms of at least 200
MHz. It may not be possible to observe high-speed noise events with a low-speed oscilloscope.
If you detect potential noise-induced malfunctions while observing the waveform with an oscilloscope, recheck
with a low-impedance (less than 1 k
) resistor connecting the relevant pin to GND or to the power supply.
Malfunctions at that pin are likely if changes are visible, such as the malfunction disappearing, becoming less
frequent, or the phenomena changing.
The DSIO and #RESET input circuits described above detect input signal edges and are susceptible to
malfunctions induced by spike noise. This makes these digital signal pins the most susceptible to noise.
To reduce potential noise, keep the following two points in mind when designing circuit boards:
(A) It is important to use low impedance resistors when driving the signals, as described above. Avoid
connecting impedance exceeding 1 k
(ideally, 0 ) to the power supply or GND. The signal lines
connected should be no longer than approximately 5 mm.
(B) Signals switching from 1 to 0 or 0 to 1 may generate noise if signal lines run parallel to other digital lines
on the circuit board.
The highest risk of noise occurs in configurations in which a line is sandwiched between multiple signal
lines that vary in synchrony. You can minimize noise effects by reducing the length of parallel sections (limit
to a few cm) or by increasing the separation (to at least 2 mm).