Appendix A: I/O Register List
S1C17601 TECHNICAL MANUAL
Seiko Epson Corporation
AP-13
0x4360–0x436c
I2C Slave
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
I2C Slave
Transmit Data
Register
(I2CS_TRNS)
0x4360
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 SDATA[7:0] I2C slave transmit data
0–0xff
0x0 R/W
I2C Slave
Receive Data
Register
(I2CS_RECV)
0x4362
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 RDATA[7:0] I2C slave receive data
0–0xff
0x0
R
I2C Slave
Address Setup
Register
(I2CS_SADRS)
0x4364
(16 bits)
D15–7 –
reserved
–
0 when being read.
D6–0 SADRS[6:0] I2C slave address
0–0x7f
0x0 R/W
I2C Slave
Control Register
(I2CS_CTL)
0x4366
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
TBUF_CLR I2CS_TRNS register clear
1 Clear state 0 Normal
0
R/W
D7
I2C_EN
I2C slave enable
1 Enable
0 Disable
0
R/W
D6
SOFTRESET Software reset
1 Reset
0 Cancel
0
R/W
D5
NAK_ANS NAK answer
1 NAK
0 ACK
0
R/W
D4
BFREQ_EN Bus free request enable
1 Enable
0 Disable
0
R/W
D3
CLKSTR_EN Clock stretch On/Off
1 On
0 Off
0
R/W
D2
NF_EN
Noise filter On/Off
1 On
0 Off
0
R/W
D1
ASDET_EN Async.address detection On/Off
1 On
0 Off
0
R/W
D0
COM_MODE I2C slave communication mode
1 Active
0 Standby
0
R/W NAK response when
standby
I2C Slave
Status Register
(I2CS_STAT)
0x4368
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7
BSTAT
Bus status transition
1 Changed
0 Unchanged
0
R
D6
–
reserved
–
0 when being read.
D5
TXUDF
Transmit data underflow
1 Occurred
0 Not occurred
0
R/W Reset by writing 1.
RXOVF
Receive data overflow
D4
BFREQ
Bus free request
1 Occurred
0 Not occurred
0
R/W
D3
DMS
Output data mismatch
1 Error
0 Normal
0
R/W
D2
ASDET
Async. address detection status
1 Detected
0 Not detected
0
R/W
D1
DA_NAK
NAK receive status
1 NAK
0 ACK
0
R/W
D0
DA_STOP
STOP condition detect
1 Detected
0 Not detected
0
R/W
I2C Slave
Access Status
Register
(I2CS_ASTAT)
0x436a
(16 bits)
D15–5 –
reserved
–
0 when being read.
D4
RXRDY
Receive data ready
1 Ready
0 Not ready
0
R
D3
TXEMP
Transmit data empty
1 Empty
0 Not empty
0
R
D2
BUSY
I2C bus status
1 Busy
0 Free
0
R
D1
SELECTED I2C slave select status
1 Selected
0 Not selected
0
R
D0
R/W
Read/write direction
1 Output
0 Input
0
R
I2C Slave
Interrupt Control
Register
(I2CS_ICTL)
0x436c
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2
BSTAT_IEN Bus status interrupt enable
1 Enable
0 Disable
0
R/W
D1
RXRDY_IEN Receive interrupt enable
1 Enable
0 Disable
0
R/W
D0
TXEMP_IEN Transmit interrupt enable
1 Enable
0 Disable
0
R/W