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参数资料
| 型号： | S29CD016G0MFAN002 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 512K X 32 FLASH 2.7V PROM, 64 ns, PBGA80 |
| 封装： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80 |
| 文件页数： | 54/81页 |
| 文件大小： | 1276K |
| 代理商： | S29CD016G0MFAN002 |
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56
S29CD-G Flash Family
S29CD-G_00_B1 March 3, 2009
Data
Sheet
(Pre limin ar y)
16.3
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,
or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, two immediately consecutive read cycles to any
address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. For asynchronous mode,
either OE# or CE# can be used to control the read cycles. For synchronous mode, the rising edge of ADV# is
used or the rising edge of clock while ADV# is Low.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use
DQ7 (See DQ7: Data# Polling on page 54).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program
command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
algorithm is complete.
Table 16.1 on page 58 shows the outputs for Toggle Bit I on DQ6. Figure 16.2 on page 57 shows the toggle
bit algorithm in flowchart form, and Reading Toggle Bits DQ6/DQ2 on page 56 explains the algorithm.
Figure 24.11 on page 70 shows the toggle bit timing diagrams. Figure 24.12 on page 70 shows the
differences between DQ2 and DQ6 in graphical form. Also see DQ2: Toggle Bit II on page 56. Figure 24.11
on page 70 shows the timing diagram for synchronous toggle bit status.
16.4
DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system performs two immediately consecutive reads at addresses within those sectors
that were selected for erasure. (For asynchronous mode, either OE# or CE# can be used to control the read
cycles. For synchronous mode, ADV# is used.) But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are
required for sector and mode information. Refer to Table 16.1 on page 58 to compare outputs for DQ2 and
DQ6.
Toggle bit algorithm in is shown in Figure 16.2 on page 57 in flowchart form, and the algorithm is explained in
on page 70 shows the toggle bit timing diagram. Figure 24.12 on page 70 shows the differences between
DQ2 and DQ6 in graphical form. Figure 24.13 on page 71 shows the timing diagram for synchronous DQ2
toggle bit status.
16.5
Reading Toggle Bits DQ6/DQ2
Refer to Figure 24.11 on page 70 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must perform two immediately consecutive reads of DQ7–DQ0 to determine whether a
toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read.
After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit
is not toggling, the device completed the program or erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
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相关代理商/技术参数 |
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| S29CD016G0MFAN003 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
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