- 您现在的位置：买卖IC网 > PDF目录299877 > S29GL032N90BFI32 (SPANSION LLC) 2M X 16 FLASH 3V PROM, 90 ns, PBGA48 PDF资料下载
参数资料
| 型号： | S29GL032N90BFI32 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封装： | 8.15 X 6.15 MM, LEAD FREE, FBGA-48 |
| 文件页数： | 9/81页 |
| 文件大小： | 3095K |
| 代理商： | S29GL032N90BFI32 |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页
October 29, 2008 S29GL-N_01_12
S29GL-N MirrorBit Flash Family
17
Data
She e t
8.
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is a latch used to store the commands, along with the address and data information needed to
execute the command. The contents of the register serve as inputs to the internal state machine. The state
machine outputs dictate the function of the device. Table 8.1 lists the device bus operations, the inputs and
control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.
Legend
L = Logic Low = VIL
H = Logic High = VIH
VHH = 11.5–12.5 V
X = Don’t Care
AIN = Address In
DIN = Data In
DOUT = Data Out
Notes
1. If WP# = VIL, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for boot sector devices). If WP#
= VIH, the first or last sector, or the two outer boot sectors are protected or unprotected as determined by the method described in Write Protect (WP#). All
sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.)
2. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 10.5 on page 56).
8.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the
BYTE# pin is set at logic 1, the device is in word configuration, DQ0–DQ15 are active and controlled by CE#,
WE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE#, WE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin
is used as an input for the LSB (A-1) address function.
8.2
Requirements for Reading Array Data
All memories require access time to output array data. In a read operation, data is read from one memory
location at a time. Addresses are presented to the device in random order, and the propagation delay through
the device causes the data on its outputs to arrive with the address on its inputs.
The device defaults to reading array data after device power-up or hardware reset. To read data from the
memory array, the system must first assert a valid address on Amax-A0, while driving OE# and CE# to VIL.
WE# must remain at VIH. All addresses are latched on the falling edge of CE#. Data will appear on
DQ15-DQ0 after address access time (tACC), which is equal to the delay from stable addresses to valid output
data. The OE# signal must be driven to VIL. Data is output on DQ15-DQ0 pins after the access time (tOE) has
elapsed from the falling edge of OE#.
See Reading Array Data on page 41 for more information. Refer to Table 15.1 on page 64 for timing
specifications and the timing diagram. Refer to Table 13.1 on page 62 for the active current specification on
reading array data.
Table 8.1 Device Bus Operations
Operation
CE#
OE#
WE#
RESET#
WP#
ACC
Addresses
DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read
LL
H
X
AIN
DOUT
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
LH
L
H
XAIN
Accelerated Program
LH
L
H
VHH
AIN
Standby
VCC ± 0.3V
X
VCC ± 0.3V
X
H
X
High-Z
Output Disable
L
H
X
High-Z
Reset
X
L
X
High-Z
相关PDF资料 |
PDF描述 |
|---|---|
| S2A | SURFACE MOUNT RECTIFIER |
| S2B | SURFACE MOUNT RECTIFIER |
| S2C1R-1-5-H | 4000 MHz - 8000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 1.7 dB INSERTION LOSS |
| S2D | SURFACE MOUNT RECTIFIER |
| S2G | SURFACE MOUNT RECTIFIER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S29GL032N90DFI020 | 功能描述:IC FLASH 32MBIT 90NS 64BGA 制造商:cypress semiconductor corp 系列:GL-N 包装:托盘 零件状态:在售 存储器类型:非易失 存储器格式:闪存 技术:FLASH - NOR 存储容量:32Mb （4M x 8，2M x 16） 写周期时间 - 字，页:90ns 访问时间:90ns 存储器接口:并联 电压 - 电源:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C（TA） 安装类型:表面贴装 封装/外壳:64-LBGA 供应商器件封装:64 球加强型 BGA（9x9） 标准包装:260 |
| S29GL032N90DFI023 | 功能描述:IC FLASH 32MBIT 90NS 64BGA 制造商:cypress semiconductor corp 系列:GL-N 包装:剪切带（CT） 零件状态:在售 存储器类型:非易失 存储器格式:闪存 技术:FLASH - NOR 存储容量:32Mb （4M x 8，2M x 16） 写周期时间 - 字，页:90ns 访问时间:90ns 存储器接口:并联 电压 - 电源:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C（TA） 安装类型:表面贴装 封装/外壳:64-LBGA 供应商器件封装:64 球加强型 BGA（9x9） 标准包装:1 |
| S29GL032N90FAI030 | 制造商:Spansion 功能描述:IC, FLASH - Trays |
| S29GL032N90FAI040 | 功能描述:闪存 32Mb 3V 90ns Parallel NOR 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| S29GL032N90FFI010 | 功能描述:闪存 32Mb 3V 90ns Parallel NOR 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。