Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
MC9S12HZ256 Data Sheet, Rev. 2.05
210
Freescale Semiconductor
.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is dened at the MCU level and the Address Offset is dened at the module
level.
Table 7-1. ATD10B16C Memory Map
Address Offset
Use
Access
0x0000
ATD Control Register 0 (ATDCTL0)
R/W
0x0001
ATD Control Register 1 (ATDCTL1)
R/W
0x0002
ATD Control Register 2 (ATDCTL2)
R/W
0x0003
ATD Control Register 3 (ATDCTL3)
R/W
0x0004
ATD Control Register 4 (ATDCTL4)
R/W
0x0005
ATD Control Register 5 (ATDCTL5)
R/W
0x0006
ATD Status Register 0 (ATDSTAT0)
R/W
0x0007
Unimplemented
0x0008
ATD Test Register 0 (ATDTEST0)1
1 ATDTEST0 is intended for factory test purposes only.
R
0x0009
ATD Test Register 1 (ATDTEST1)
R/W
0x000A
ATD Status Register 2 (ATDSTAT2)
R
0x000B
ATD Status Register 1 (ATDSTAT1)
R
0x000C
ATD Input Enable Register 0 (ATDDIEN0)
R/W
0x000D
ATD Input Enable Register 1 (ATDDIEN1)
R/W
0x000E
Port Data Register 0 (PORTAD0)
R
0x000F
Port Data Register 1 (PORTAD1)
R
0x0010, 0x0011
ATD Result Register 0 (ATDDR0H, ATDDR0L)
R/W
0x0012, 0x0013
ATD Result Register 1 (ATDDR1H, ATDDR1L)
R/W
0x0014, 0x0015
ATD Result Register 2 (ATDDR2H, ATDDR2L)
R/W
0x0016, 0x0017
ATD Result Register 3 (ATDDR3H, ATDDR3L)
R/W
0x0018, 0x0019
ATD Result Register 4 (ATDDR4H, ATDDR4L)
R/W
0x001A, 0x001B
ATD Result Register 5 (ATDDR5H, ATDDR5L)
R/W
0x001C, 0x001D
ATD Result Register 6 (ATDDR6H, ATDDR6L)
R/W
0x001E, 0x001F
ATD Result Register 7 (ATDDR7H, ATDDR7L)
R/W
0x0020, 0x0021
ATD Result Register 8 (ATDDR8H, ATDDR8L)
R/W
0x0022, 0x0023
ATD Result Register 9 (ATDDR9H, ATDDR9L)
R/W
0x0024, 0x0025
ATD Result Register 10 (ATDDR10H, ATDDR10L)
R/W
0x0026, 0x0027
ATD Result Register 11 (ATDDR11H, ATDDR11L)
R/W
0x0028, 0x0029
ATD Result Register 12 (ATDDR12H, ATDDR12L)
R/W
0x002A, 0x002B
ATD Result Register 13 (ATDDR13H, ATDDR13L)
R/W
0x002C, 0x002D
ATD Result Register 14 (ATDDR14H, ATDDR14L)
R/W
0x002E, 0x002F
ATD Result Register 15 (ATDDR15H, ATDDR15L)
R/W