Chapter 4 Port Integration Module (PIM9HZ256V2)
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
149
4.3.6.2
Port T Input Register (PTIT)
Read: Anytime. Write: Never, writes to this register have no effect.
If the LCD frontplane driver of an associated I/O pin is enabled (and LCD module is enabled), a read
returns a 1.
If the LCD frontplane driver of the associated I/O pin is disabled (or LCD module is disabled), a read
returns the status of the associated pin.
4.3.6.3
Port T Data Direction Register (DDRT)
Read: Anytime. Write: Anytime.
This register configures port pins PT[7:0] as either input or output.
If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the
corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver
is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control
the I/O direction of the associated pin.
If the TIM module is enabled, each port pin configured for output compare is forced to be an output and
the associated Data Direction Register bit has no effect. If the associated timer output compare is disabled,
the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
If the TIM module is enabled, each port pin configured as an input capture has the corresponding Data
Direction Register bit controlling the I/O direction of the associated pin.
76543210
R
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
W
Reset
u
uuuuu
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-38. Port T Input Register (PTIT)
76543210
R
DDRT7
DDRT6
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
W
Reset
0
00000
Figure 4-39. Port T Data Direction Register (DDRT)
Table 4-28. DDRT Field Descriptions
Field
Description
7:0
DDRT[7:0]
Data Direction Port T
0 Associated pin is congured as input.
1 Associated pin is congured as output.