Chapter 10 Stepper Stall Detector (SSDV1)
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
301
10.3.2.6
Integration Accumulator Register (ITGACC)
Read: anytime.
Write: Never.
NOTE
A separate read for high byte and low byte gives a different result than
accessing the register as a word.
This 16-bit eld is signed and is represented in two’s complement. It indicates the change in ux while
integrating the back EMF present in the non-driven coil during a return to zero event.
When ITG is zero, the accumulator is initialized to 0x0000 and the sigma-delta converter is in a reset state.
When ITG is one, the accumulator increments or decrements depending on the sigma-delta conversion
sample. The accumulator sample frequency is determined by the ACLKS eld. The accumulator freezes
at 0x7FFF on a positive overow and freezes at 0x8000 on a negative overow.
10.4
Functional Description
The stepper stall detector (SSD) has a simple control block to congure the H-bridge drivers of a stepper
motor in four different full step states with four available modes during a return to zero event. The SSD
has a detect circuit using a sigma-delta converter to measure and integrate changes in ux of the
de-energized winding in the stepping motor and the conversion result is accumulated in a 16-bit signed
register. The SSD also has a 16-bit modulus down counter to monitor blanking and integration times. DC
offset compensation is implemented when using the modulus down counter to monitor integration times.
10.4.1
Return to Zero Modes
There are four return to zero modes as shown in
Table 10-11.
15
14
13
12
11
10
9
8
R
ITGACC
W
Reset
0
00000
Figure 10-8. Integration Accumulator Register High (ITGACC)
76543210
R
ITGACC
W
Reset
0
00000
Figure 10-9. Integration Accumulator Register Low (ITGACC)
Table 10-11. Return to Zero Modes
ITG
DCOIL
Mode