Chapter 21 Multiplexed External Bus Interface (MEBIV3)
MC9S12HZ256 Data Sheet, Rev. 2.05
596
Freescale Semiconductor
21.3.2.16 Port K Data Direction Register (DDRK)
Read: Anytime
Write: Anytime
This register determines the primary direction for each port K pin congured as general-purpose I/O. This
register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is
set. Therefore, these accesses will be echoed externally.
21.4
Functional Description
21.4.1
Detecting Access Type from External Signals
The external signals LSTRB, R/W, and AB0 indicate the type of bus access that is taking place. Accesses
to the internal RAM module are the only type of access that would produce LSTRB = AB0 = 1, because
the internal RAM is specically designed to allow misaligned 16-bit accesses in a single cycle. In these
cases the data for the address that was accessed is on the low half of the data bus and the data for
address + 1 is on the high half of the data bus. This is summarized in
Table 21-15.
76543210
R
Bit 7
654321
Bit 0
W
Reset
00000000
Figure 21-20. Port K Data Direction Register (DDRK)
Table 21-14. EBICTL Field Descriptions
Field
Description
7:0
DDRK
Data Direction Port K Bits
0 Associated pin is a high-impedance input
1 Associated pin is an output
Note: It is unwise to write PORTK and DDRK as a word access. If you are changing port K pins from inputs to
outputs, the data may have extra transitions during the write. It is best to initialize PORTK before enabling
as outputs.
Note: To ensure that you read the correct value from the PORTK pins, always wait at least one cycle after writing
to the DDRK register before reading from the PORTK register.
Table 21-15. Access Type vs. Bus Control Pins
LSTRB
AB0
R/W
Type of Access
1
0
1
8-bit read of an even address
0
1
8-bit read of an odd address
1
0
8-bit write of an even address
0
1
0
8-bit write of an odd address
0
1
16-bit read of an even address