Chapter 10 Stepper Stall Detector (SSDV1)
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
297
10.3.2.2
Modulus Down Counter Control Register (MDCCTL)
Read: anytime
Write: anytime.
l
Table 10-6. Full Step States
STEP
Pole
Angle
COSINE
Coil Current
SINE
Coil Current
Coil Node to
Integrator input
(Close Switch)
Coil Node to
Reference input
(Close Switch)
DCOIL = 0 DCOIL = 1 DCOIL = 0 DCOIL = 1
ITG = 1
POL = 0
ITG = 1
POL = 1
ITG = 1
POL = 0
ITG = 1
POL = 1
0
East
0
°
0
+ I max
0
SINxM (S8)
SINxP (S6)
SINxP (S5)
SINxM (S7)
1
North
90
°
0
+ I max
COSxP (S2) COSxM (S4) COSxM (S3) COSxP (S1)
2
West
180
°
0
– I max
0
SINxP (S6)
SINxM (S8)
SINxM (S7)
SINxP (S5)
3
South
270
°
0
– I max
COSxM (S4) COSxP (S2) COSxP (S1) COSxM (S3)
76543210
R
MCZIE
MODMC
RDMCL
PRE
0
MCEN
0
AOVIE
W
FLMC
Reset
0
00000
= Unimplemented or Reserved
Figure 10-3. Modulus Down Counter Control Register (MDCCTL)
Table 10-7. MDCCTL Field Descriptions
Field
Description
7
MCZIE
Modulus Counter Underow Interrupt Enable
0 Interrupt disabled.
1 Interrupt enabled. An interrupt will be generated when the modulus counter underow interrupt ag (MCZIF)
is set.
6
MODMC
Modulus Mode Enable
0 The modulus counter counts down from the value in the counter register and will stop at 0x0000.
1 Modulus mode is enabled. When the counter reaches 0x0000, the counter is loaded with the latest value
written to the modulus counter register.
Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset
the modulus counter to 0xFFFF.
5
RDMCL
Read Modulus Down-Counter Load
0 Reads of the modulus count register (MDCCNT) will return the present value of the count register.
1 Reads of the modulus count register (MDCCNT) will return the contents of the load register.
4
PRE
Prescaler
0 The modulus down counter clock frequency is the bus frequency divided by 64.
1 The modulus down counter clock frequency is the bus frequency divided by 512.
Note: A change in the prescaler division rate will not be effective until a load of the load register into the modulus
counter count register occurs.