Chapter 5 Clocks and Reset Generator (CRGV4)
MC9S12HZ256 Data Sheet, Rev. 2.05
180
Freescale Semiconductor
5.3.2.9
CRG COP Control Register (COPCTL)
This register controls the COP (computer operating properly) watchdog.
Read: anytime
Write: WCOP, CR2, CR1, CR0: once in user mode, anytime in special mode
Write: RSBCK: once
76543210
R
WCOP
RSBCK
000
CR2
CR1
CR0
W
Reset
0
00000
= Unimplemented or Reserved
Figure 5-12. CRG COP Control Register (COPCTL)
Table 5-8. COPCTL Field Descriptions
Field
Description
7
WCOP
Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected
period. A write during the rst 75% of the selected period will reset the part. As long as all writes occur during
this window, 0x0055 can be written as often as desired. As soon as 0x00AA is written after the 0x0055, the
time-out logic restarts and the user must wait until the next window before writing to ARMCOP.
Table 5-9 shows
the exact duration of this window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
6
RSBCK
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in active BDM mode.
1 Stops the COP and RTI counters whenever the part is in active BDM mode.
2:0
CR[2:0]
COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see
Table 5-9). The COP
time-out period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the COP
counter and starts the time-out period. A COP counter time-out causes a system reset. This can be avoided by
periodically (before time-out) reinitializing the COP counter via the ARMCOP register.
Table 5-9. COP Watchdog Rates1
1 OSCCLK cycles are referenced from the previous COP time-out reset
(writing 0x0055/0x00AA to the ARMCOP register)
CR2
CR1
CR0
OSCCLK
Cycles to Time Out
0
COP disabled
001
214
010
216
011
218
100
220
101
222
110
223
111
224