Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
MC9S12HZ256 Data Sheet, Rev. 2.05
460
Freescale Semiconductor
Read: anytime
Write: anytime
15.3.2.14 PWM Channel Duty Registers (PWMDTYx)
There is a dedicated duty register for each channel. The value in this register determines the duty of the
associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value
a match occurs and the output changes state.
The duty registers for each channel are double buffered so that if they change while the channel is enabled,
the change will NOT take effect until one of the following occurs:
The effective period ends
The counter is written (counter resets to 0x0000)
The channel is disabled
In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform,
not some variation in between. If the channel is not enabled, then writes to the duty register will go directly
to the latches as well as the buffer.
NOTE
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active duty due to the double
buffering scheme.
NOTE
Depending on the polarity bit, the duty registers will contain the count of
either the high time or the low time. If the polarity bit is 1, the output starts
high and then goes low when the duty count is reached, so the duty registers
contain a count of the high time. If the polarity bit is 0, the output starts low
and then goes high when the duty count is reached, so the duty registers
contain a count of the low time.
To calculate the output duty cycle (high time as a % of period) for a particular channel:
Polarity = 0 (PPOLx = 0)
Duty cycle = [(PWMPERx PWMDTYx)/PWMPERx] * 100%
Polarity = 1 (PPOLx = 1)
Duty cycle = [PWMDTYx / PWMPERx] * 100%
76543210
R
Bit 7
6
5
4321
Bit 0
W
Reset
0
00000
Figure 15-26. PWM Channel Period Registers (PWMPER5)