Chapter 1 MC9S12HZ256 Device Overview
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
53
0xFFF2, 0xFFF3
IRQ
I-Bit
INTCR (IRQEN)
0xF2
0xFFF0, 0xFFF1
Real Time Interrupt
I-Bit
RTICTL (RTIE)
0xF0
0xFFEE, 0xFFEF
Timer channel 0
I-Bit
TIE (C0I)
0xEE
0xFFEC, 0xFFED
Timer channel 1
I-Bit
TIE (C1I)
0xEC
0xFFEA, 0xFFEB
Timer channel 2
I-Bit
TIE (C2I)
0xEA
0xFFE8, 0xFFE9
Timer channel 3
I-Bit
TIE (C3I)
0xE8
0xFFE6, 0xFFE7
Timer channel 4
I-Bit
TIE (C4I)
0xE6
0xFFE4, 0xFFE5
Timer channel 5
I-Bit
TIE (C5I)
0xE4
0xFFE2, 0xFFE3
Timer channel 6
I-Bit
TIE (C6I)
0xE2
0xFFE0, 0xFFE1
Timer channel 7
I-Bit
TIE (C7I)
0xE0
0xFFDE, 0xFFDF
Timer overow
I-Bit
TSCR2 (TOI)
0xDE
0xFFDC, 0xFFDD
Pulse accumulator A overow
I-Bit
PACTL (PAOVI)
0xDC
0xFFDA, 0xFFDB
Pulse accumulator input edge
I-Bit
PACTL (PAI)
0xDA
0xFFD8, 0xFFD9
SPI
I-Bit
SPCR1 (SPIE)
0xD8
0xFFD6, 0xFFD7
SCI0
I-Bit
SC0CR2
(TIE, TCIE, RIE, ILIE)
0xD6
0xFFD4, 0xFFD5
SCI1
I-Bit
SC1CR2
(TIE, TCIE, RIE, ILIE)
0xD4
0xFFD2, 0xFFD3
ATD
I-Bit
ATDCTL2 (ASCIE)
0xD2
0xFFD0, 0xFFD1
Reserved
I-Bit
Reserved
0xD0
0xFFCE, 0xFFCF
Reserved
I-Bit
Reserved
0xCE
0xFFCC, 0xFFCD
Reserved
I-Bit
Reserved
0xCC
0xFFCA, 0xFFCB
Reserved
I-Bit
Reserved
0xCA
0xFFC8, 0xFFC9
Port AD
I-Bit
PTADIF (PTADIE)
0xC8
0xFFC6, 0xFFC7
CRG PLL lock
I-Bit
CRGINT (LOCKIE)
0xC6
0xFFC4, 0xFFC5
CRG Self Clock Mode
I-Bit
CRGINT (SCMIE)
0xC4
0xFFC2, 0xFFC3
Reserved
I-Bit
Reserved
0xC2
0xFFC0, 0xFFC1
IIC Bus
I-Bit
IBCR (IBIE)
0xC0
0xFFBE, 0xFFBF
Reserved
I-Bit
Reserved
0xBE
0xFFBC, 0xFFBD
Reserved
I-Bit
Reserved
0xBC
0xFFBA, 0xFFBB
EEPROM
I-Bit
EECTL (CCIE, CBEIE)
0xBA
0xFFB8, 0xFFB9
FLASH
I-Bit
FCTL (CCIE, CBEIE)
0xB8
0xFFB6, 0xFFB7
CAN0 wake-up
I-Bit
CAN0RIER (WUPIE)
0xB6
0xFFB4, 0xFFB5
CAN0 errors
I-Bit
CAN0RIER (CSCIE, OVRIE)
0xB4
0xFFB2, 0xFFB3
CAN0 receive
I-Bit
CAN0RIER (RXFIE)
0xB2
0xFFB0, 0xFFB1
CAN0 transmit
I-Bit
CAN0TIER (TXEIE[2:0])
0xB0
0xFFAE, 0xFFAF
CAN1 wake-up
I-Bit
CAN1RIER (WUPIE)
0xAE
0xFFAC, 0xFFAD
CAN1 errors
I-Bit
CAN1RIER (CSCIE, OVRIE)
0xAC
0xFFAA, 0xFFAB
CAN1 receive
I-Bit
CAN1RIER (RXFIE)
0xAA
Table 1-11. Interrupt Vector Locations (continued)
Vector Address
Interrupt Source
CCR
Mask
Local Enable
HPRIO Value
to Elevate