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参数资料
| 型号： | SC16C2552BIA44,512 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 35/37页 |
| 文件大小： | 0K |
| 描述： | IC UART DUAL SOT187-2 |
| 标准包装： | 26 |
| 特点： | 2 通道 |
| 通道数： | 2，DUART |
| FIFO's： | 16 字节 |
| 电源电压： | 2.5V，3.3V，5V |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC |
| 包装： | 管件 |
| 其它名称： | 935274408512 SC16C2552BIA44 SC16C2552BIA44-ND |
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SC16C2552B_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 February 2009
7 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.2 Internal registers
The SC16C2552B provides two sets of internal registers (A and B) consisting of
13 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in Table 4. The UART registers function as data holding
registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control
register (FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), a
user accessible scratchpad register (SPR), and an Alternate Function Register (AFR).
[1]
The baud rate register and AFR register sets are accessible only when CS is a logic 0 and LCR[7] is a
logic 1 for the register set (A/B) being accessed.
6.3 FIFO operation
The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register
(FCR) bit 0. The user can set the receive trigger level via FCR[7:6], but not the transmit
trigger level. The receiver FIFO section includes a time-out function to ensure data is
delivered to the external CPU. A time-out interrupt is generated whenever the Receive
Holding Register (RHR) has not been read following the loading of a character, or the
receive trigger interrupt is generated when RX FIFO level is equal to the program RX
trigger value.
6.4 Time-out interrupts
The interrupts are enabled by IER[3:0]. Care must be taken when handling these
interrupts. Following a reset, if the transmitter interrupt is enabled, the SC16C2552B will
issue an interrupt to indicate that the Transmit Holding Register is empty. The ISR register
provides the current singular highest priority interrupt only. A condition can exist where a
higher priority interrupt may mask the lower priority interrupt(s). Only after servicing the
higher pending interrupt will the lower priority interrupt(s) be reected in the status
register. Servicing the interrupt without investigating further interrupt conditions can result
in data errors.
Table 4.
Internal registers decoding
A2
A1
A0
Read mode
Write mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)
0
Receive Holding Register
Transmit Holding Register
0
1
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
Line Control Register
1
0
Modem Control Register
1
0
1
Line Status Register
n/a
1
0
Modem Status Register
n/a
1
Scratchpad Register
Baud rate register set (DLL/DLM, AFR)[1]
0
LSB of Divisor Latch
0
1
MSB of Divisor Latch
0
1
0
Alternate Function Register
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SC16C2552BIA44-T | 功能描述:UART 接口集成电路 16CB 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C2552CIA44,512 | 制造商:NXP Semiconductors 功能描述: 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/TUBEDP// - Rail/Tube |
| SC16C2552CIA44,518 | 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/REEL13DP// - Tape and Reel |
| SC16C2552CIA44,529 | 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/TUBESMDP// - Rail/Tube |
| SC16C2552IA44 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Dual UART with 16-byte transmit and receive FIFOs |
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