- 您现在的位置：买卖IC网 > PDF目录11825 > SC16C2552BIA44,512 (NXP Semiconductors)IC UART DUAL SOT187-2 PDF资料下载
参数资料
| 型号： | SC16C2552BIA44,512 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 5/37页 |
| 文件大小： | 0K |
| 描述： | IC UART DUAL SOT187-2 |
| 标准包装： | 26 |
| 特点： | 2 通道 |
| 通道数： | 2，DUART |
| FIFO's： | 16 字节 |
| 电源电压： | 2.5V，3.3V，5V |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC |
| 包装： | 管件 |
| 其它名称： | 935274408512 SC16C2552BIA44 SC16C2552BIA44-ND |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页
SC16C2552B_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 February 2009
13 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1) and receive interrupts (IER[0] = logic 1) are
enabled, the receive interrupts and register status will reect the following:
The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
Receive FIFO status will also be reected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit and
the interrupt will be cleared when the FIFO drops below the trigger level.
The receive data ready bit (LSR[0]) is set as soon as a character is transferred from
the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.
When the Transmit FIFO and interrupts are enabled, an interrupt is generated when
the transmit FIFO is empty due to the unloading of the data by the TSR and UART for
transmission via the transmission media. The interrupt is cleared either by reading the
ISR register or by loading the THR with new data characters.
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C2552B in the FIFO polled
mode of operation. In this mode, interrupts are not generated and the user must poll the
LSR register for TX and/or RX data status. Since the receiver and transmitter have
separate bits in the LSR either or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[4:1] will provide the type of receive errors or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will show if any FIFO data errors occurred.
相关PDF资料 |
PDF描述 |
|---|---|
| SC16C652BIBS,157 | IC UART DUAL W/FIFO 32HVQFN |
| VI-23R-IY | CONVERTER MOD DC/DC 7.5V 50W |
| SC16C852VIET,157 | IC UART DUAL W/FIFO 36TFBGA |
| MS3102R32-8S | CONN RCPT 30POS BOX MNT W/SCKT |
| MS3102E32-8S | CONN RCPT 30POS BOX MNT W/SCKT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SC16C2552BIA44-T | 功能描述:UART 接口集成电路 16CB 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C2552CIA44,512 | 制造商:NXP Semiconductors 功能描述: 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/TUBEDP// - Rail/Tube |
| SC16C2552CIA44,518 | 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/REEL13DP// - Tape and Reel |
| SC16C2552CIA44,529 | 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/TUBESMDP// - Rail/Tube |
| SC16C2552IA44 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Dual UART with 16-byte transmit and receive FIFOs |
发布紧急采购，3分钟左右您将得到回复。