参数资料
型号: SC16C2552BIA44,512
厂商: NXP Semiconductors
文件页数: 8/37页
文件大小: 0K
描述: IC UART DUAL SOT187-2
标准包装: 26
特点: 2 通道
通道数: 2,DUART
FIFO's: 16 字节
电源电压: 2.5V,3.3V,5V
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC
包装: 管件
其它名称: 935274408512
SC16C2552BIA44
SC16C2552BIA44-ND
SC16C2552B_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 February 2009
16 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.4 Interrupt Status Register (ISR)
The SC16C2552B provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged until
the pending interrupt is serviced. Whenever the interrupt status register is read, the
interrupt status is cleared. However, it should be noted that only the current pending
interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the
interrupt status bits. Table 10 shows the data values (bits 3:0) for the four prioritized
interrupt levels and the interrupt sources associated with each of these interrupt levels.
Table 10.
Interrupt source
Priority
level
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Received Data Ready)
2
1
0
RXRDY (Receive Data Time-out)
3
0
1
0
TXRDY (Transmitter Holding Register empty)
4
0
MSR (Modem Status Register)
Table 11.
Interrupt Status Register bits description
Bit
Symbol
Description
7:6
ISR[7:6]
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being
used in the 16C450 mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C2552B mode.
logic 0 or cleared = default condition
5:4
ISR[5:4]
not used; initialized to a logic 0
3:1
ISR[3:1]
INT priority bits. These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2 and 3 (see Table 10).
0
ISR[0]
INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
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SC16C2552CIA44,512 制造商:NXP Semiconductors 功能描述: 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/TUBEDP// - Rail/Tube
SC16C2552CIA44,518 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/REEL13DP// - Tape and Reel
SC16C2552CIA44,529 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/TUBESMDP// - Rail/Tube
SC16C2552IA44 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Dual UART with 16-byte transmit and receive FIFOs