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参数资料
| 型号： | SC16C2552BIA44,512 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 7/37页 |
| 文件大小： | 0K |
| 描述： | IC UART DUAL SOT187-2 |
| 标准包装： | 26 |
| 特点： | 2 通道 |
| 通道数： | 2，DUART |
| FIFO's： | 16 字节 |
| 电源电压： | 2.5V，3.3V，5V |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC |
| 包装： | 管件 |
| 其它名称： | 935274408512 SC16C2552BIA44 SC16C2552BIA44-ND |
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SC16C2552B_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 February 2009
15 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
3
(continued)
Transmit operation in mode ‘1’: When the SC16C2552B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic 0 if
one or more FIFO locations are empty.
Receive operation in mode ‘1’: When the SC16C2552B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-out has occurred, the RXRDY signal at the
MFn pin will go to a logic 0. Once activated, it will go to a logic 1 after
there are no more characters in the FIFO. Note that the AFR register
must be set to the RXRDY mode prior to any possible reading of the
RXRDY signal.
2
FCR[2]
XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the Transmit Shift Register is not cleared or altered).
This bit will return to a logic 0 after clearing the FIFO.
1
FCR[1]
RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the Receive Shift Register is not cleared or altered).
This bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFOs enabled.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’
when other FCR bits are written to or they will not be
programmed.
Table 9.
RCVR trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level
0001
0104
1008
1114
Table 8.
FIFO Control Register bits description …continued
Bit
Symbol
Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SC16C2552BIA44-T | 功能描述:UART 接口集成电路 16CB 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C2552CIA44,512 | 制造商:NXP Semiconductors 功能描述: 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/TUBEDP// - Rail/Tube |
| SC16C2552CIA44,518 | 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/REEL13DP// - Tape and Reel |
| SC16C2552CIA44,529 | 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/TUBESMDP// - Rail/Tube |
| SC16C2552IA44 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Dual UART with 16-byte transmit and receive FIFOs |
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