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| 型号： | SC9RS08KA1J3CDB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO6 |
| 封装： | 3 X 3 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, DFN-6 |
| 文件页数： | 115/134页 |
| 文件大小： | 3114K |
| 代理商： | SC9RS08KA1J3CDB |
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Internal Clock Source (RS08ICSV1)
SC9RS08KA2 Series Data Sheet, Rev. 1
Freescale Semiconductor
81
9.4.1.4
Stop
ICS stop mode is entered whenever the MCU enters stop. In this mode, all ICS clocks are stopped except
ICSIRCLK which will remaining running if IREFSTEN is written to a 1.
When the MCU is interrupted from stop, the ICS will go back to the operating mode that was running when
the MCU entered stop. If the internal reference was not running in stop (IREFSTEN = 0), the ICS will take
some time, tir_wu, for the internal reference to wakeup. If the internal reference was already running in stop
(IREFSTEN = 1), entering into FEI will take some time, tfll_wu, for the FLL to return its previous acquired
frequency.
9.4.2
Mode Switching
When changing from FBILP to either FEI or FBI, or anytime the trim value is written, the user should wait
the FLL acquisition time, tacquire, before FLL will be guaranteed to be at desired frequency.
9.4.3
Bus Frequency Divider
The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur
immediately.
9.4.4
Low Power Bit Usage
The low power bit (LP) is provided to allow the FLL to be disabled and thus conserve power when it is
not being used. However, in some applications it may be desirable to enable the FLL and allow it to lock
for maximum accuracy before switching to an FLL engaged mode. The FLL is disabled in bypass mode
when LP = 1.
9.4.5
Internal Reference Clock
The ICSIRCLK frequency can be re-targeted by trimming the period of the internal reference clock. This
can be done by writing a new value to the TRIM bits in the ICSTRM register. Writing a larger value will
slow down the ICSIRCLK frequency, and writing a smaller value to the ICSTRM register will speed up
the ICSIRCLK frequency. The TRIM bits will affect the ICSOUT frequency if the ICS is in FLL engaged
internal (FEI), FLL bypassed internal (FBI), or FLL bypassed internal low power (FBILP) mode. The
TRIM and FTRIM values will not be affected by a reset. For the ICS to run in stop, the LVDE and LVDSE
bits in the SPMSC1 must both be set before entering stop.
Until ICSIRCLK is trimmed, ICSOUT frequencies may exceed the maximum chip-level frequency and
violate the chip-level clock timing specifications (see the Device Overview chapter). The BDIV is reset to
a divide by 2 to prevent the bus frequency from exceeding the maximum. The user should trim the device
to an allowable frequency before changing BDIV to a divide by 1 operation.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SC9RS08KA1J3CPC | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:RS08 Microcontrollers |
| SC9RS08KA1J3CSC | 制造商:Freescale Semiconductor 功能描述:8-BIT RS08 CISC 1KB FLASH 2.5V/3.3V/5V 8-PIN SOIC N RAIL - Rail/Tube 制造商:Freescale Semiconductor 功能描述:1K FLASH W/ ACMP 62 RAM |
| SC9RS08KA2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:RS08 Microcontrollers |
| SC9RS08KA2J3CDB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:RS08 Microcontrollers |
| SC9RS08KA2J3CPC | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:RS08 Microcontrollers |
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