MC68336/376
CONFIGURABLE TIMER MODULE 4
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
10-9
10.7.2.1 Loading the MCSM Counter Register
The MCSM counter is loaded either by writing to the counter register or by loading it
from the modulus latch when a counter overflow occurs. Counter overflow will set the
COF bit in the MCSM status/interrupt/control register (MCSMSIC).
NOTE
When the modulus latch is loaded with $FFFF, the overflow flag is set
on every counter clock pulse.
10.7.2.2 Using the MCSM as a Free-Running Counter
Although the MCSM is a modulus counter, it can operate like a free-running counter
by loading the modulus register with $0000.
10.7.3 MCSM Clock Sources
The MCSM has eight software selectable counter clock sources, including:
Six CPSM prescaler outputs (PCLK[1:6])
Rising edge on the CTM2C input
Falling edge on the CTM2C input
The clock source is selected by the CLK[2:0] bits in MCSMSIC. When the CLK[2:0]
bits are being changed, internal circuitry guarantees that spurious edges occurring on
the CTM2C pin do not affect the MCSM. The read only IN2 bit in MCSMSIC reflects
the state of CTM2C. This pin is Schmitt-triggered, and is synchronized with the system
clock. The maximum allowable frequency for a clock signal input on CTM2C is fsys/4.
10.7.4 MCSM External Event Counting
When an external clock source is selected, the MCSM can act as an event counter
simply by counting the number of events occurring on the CTM2C input pin. Alterna-
tively, the MCSM can be programmed to generate an interrupt when a predefined
number of events have been counted. This is done by presetting the counter with the
two’s complement value of the desired number of events.
10.7.5 MCSM Time Base Bus Driver
The DRVA and DRVB bits in MCSMSIC select the time base bus to be driven. Which
of the time base buses is driven depends on where the MCSM is physically placed in
information.
WARNING
Two time base buses should not be driven at the same time.
10.7.6 MCSM Interrupts
The MCSM can optionally request an interrupt when its counter overflows and the
COF bit in MCSMSIC is set. To enable interrupts, set the IL[2:0] field in the MCSMSIC
to a non-zero value. The CTM4 compares the CPU32 IP mask value to the priority of