MC68336/376
SYSTEM INTEGRATION MODULE
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
5-55
Chip-select assertion can be synchronized with bus control signals to provide output
enable, read/write strobe, or interrupt acknowledge signals. Chip-select logic can also
generate DSACK and AVEC signals internally. A single DSACK generator is shared
by all chip-selects. Each signal can also be synchronized with the ECLK signal avail-
able on ADDR23.
When a memory access occurs, chip-select logic compares address space type,
address, type of access, transfer size, and interrupt priority (in the case of interrupt
acknowledge) to parameters stored in chip-select registers. If all parameters match,
the appropriate chip-select signal is asserted. Select signals are active low.
If a chip-select function is given the same address as a microcontroller module or an
internal memory array, an access to that address goes to the module or array, and the
chip-select signal is not asserted. The external address and data buses do not reflect
the internal access.
All chip-select circuits are configured for operation out of reset. However, all chip-
select signals except CSBOOT are disabled, and cannot be asserted until the
BYTE[1:0] field in the corresponding option register is programmed to a non-zero
value to select a transfer size. The chip-select option register must not be written until
a base address has been written to a proper base address register. Alternate functions
for chip-select pins are enabled if appropriate data bus pins are held low at the release
5-20 is a functional diagram of a single chip-select circuit.
Figure 5-20 Chip-Select Circuit Block Diagram
5.9.1 Chip-Select Registers
Each chip-select pin can have one or more functions. Chip-select pin assignment reg-
isters CSPAR[0:1] determine functions of the pins. Pin assignment registers also
CHIP SEL BLOCK
AVEC
GENERATOR
DSACK
GENERATOR
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
BASE ADDRESS REGISTER
TIMING
AND
CONTROL
ADDRESS COMPARATOR
OPTION COMPARE
OPTION REGISTER
AVEC
DSACK
PIN
BUS CONTROL
INTERNAL
SIGNALS
ADDRESS