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MC68336/376
SYSTEM INTEGRATION MODULE
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
5-34
or after DSACK (case 4), and HALT remains negated; BERR is negated at the
same time or after DSACK.
Retry Termination
— HALT and BERR are asserted in lieu of, at the same time as, or before DSACK
(case 5) or after DSACK (case 6); BERR is negated at the same time or after
DSACK; HALT may be negated at the same time or after BERR.
Table 5-13 shows various combinations of control signal sequences and the resulting
bus cycle terminations.
To control termination of a bus cycle for a retry or a bus error condition properly,
DSACK, BERR, and HALT must be asserted and negated with the rising edge of the
MCU clock. This ensures that when two signals are asserted simultaneously, the
required setup time and hold time for both of them are met for the same falling edge
timing requirements. External circuitry that provides these signals must be designed
with these constraints in mind, or else the internal bus monitor must be used.
DSACK, BERR, and HALT may be negated after AS is negated.
Table 5-13 DSACK, BERR, and HALT Assertion Results
Case
Number
Control Signal
Asserted on Rising
Edge of State
Result
N1
NOTES:
1. N = The number of current even bus state (S2, S4, etc.).
N + 2
1
DSACK
BERR
HALT
A2
NA3
NA
2. A = Signal is asserted in this bus state.
3. NA = Signal is not asserted in this state.
S4
NA
X5
4. X = Don’t care.
5. S = Signal was asserted in previous state and remains asserted in this state.
Normal termination.
2
DSACK
BERR
HALT
A
NA
A/S
S
NA
S
Halt termination: normal cycle terminate and halt.
Continue when HALT is negated.
3
DSACK
BERR
HALT
NA/A
A
NA
X
S
X
Bus error termination: terminate and take bus error
exception, possibly deferred.
4
DSACK
BERR
HALT
A
NA
X
S
NA
Bus error termination: terminate and take bus error
exception, possibly deferred.
5
DSACK
BERR
HALT
NA/A
A
A/S
X
S
Retry termination: terminate and retry when HALT is
negated.
6
DSACK
BERR
HALT
A
NA
X
A
Retry termination: terminate and retry when HALT is
negated.