MC68336/376
REGISTER SUMMARY
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
D-31
CIE1 — Queue 1 Completion Interrupt Enable
CIE1 enables completion interrupts for queue 1. The interrupt request is generated
when the conversion is complete for the last CCW in queue 1.
0 = Queue 1 completion interrupts disabled.
1 = Generate an interrupt request after completing the last CCW in queue 1.
PIE1 — Queue 1 Pause Interrupt Enable
PIE1 enables pause interrupts for queue 1. The interrupt request is generated when
the conversion is complete for a CCW that has the pause bit set.
0 = Queue 1 pause interrupts disabled.
1 = Generate an interrupt request after completing a CCW in queue 1 which has
the pause bit set.
SSE1 — Queue 1 Single-Scan Enable
SSE1 enables a single-scan of queue 1 after a trigger event occurs. The SSE1 bit may
be set to a one during the same write cycle that sets the MQ1[2:0] bits for the single-
scan queue operating mode. The single-scan enable bit can be written as a one or a
zero, but is always read as a zero.
The SSE1 bit allows a trigger event to initiate queue execution for any single-scan op-
eration on queue 1. The QADC clears SSE1 when the single-scan is complete.
MQ1[2:0] — Queue 1 Operating Mode
The MQ1 field selects the queue operating mode for queue 1. Table D-25 shows the
different queue 1 operating modes.
QACR1 — Control Register 1
$YFF20C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CIE1
PIE1
SSE1
NOT USED
MQ1[2:0]
RESERVED
RE-
SET:
0
Table D-25 Queue 1 Operating Modes
MQ1[2:0]
Queue 1 Operating Mode
000
Disabled mode, conversions do not occur
001
Software triggered single-scan mode (started with SSE1)
010
External trigger rising edge single-scan mode (on ETRIG1 pin)
011
External trigger falling edge single-scan mode (on ETRIG1 pin)
100
Reserved mode, conversions do not occur
101
Software triggered continuous-scan mode (started with SSE1)
110
External trigger rising edge continuous-scan mode (on ETRIG1 pin)
111
External trigger falling edge continuous-scan mode (on ETRIG1 pin)