MC68336/376
SYSTEM INTEGRATION MODULE
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
5-11
field in chip-select pin assignment register 1 (CSPAR1). ECLK operation during low-
power stop is described in the following paragraph. Refer to 5.9 Chip-Selects for
more information about the external bus clock.
5.3.4 Low-Power Operation
Low-power operation is initiated by the CPU32. To reduce power consumption selec-
tively, the CPU can set the STOP bits in each module configuration register. To
minimize overall microcontroller power consumption, the CPU can execute the
LPSTOP instruction, which causes the SIM to turn off the system clock.
When individual module STOP bits are set, clock signals inside each module are
turned off, but module registers are still accessible.
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of the
current interrupt mask into the clock control logic. The SIM brings the MCU out of low-
power stop mode when one of the following exceptions occur:
U-bus interface
RESET
Trace
SIM interrupt of higher priority than the stored interrupt mask
for more information.
During low-power stop mode, unless the system clock signal is supplied by an external
source and that source is removed, the SIM clock control logic and the SIM clock sig-
nal (SIMCLK) continue to operate. The periodic interrupt timer and input logic for the
RESET and IRQ pins are clocked by SIMCLK, and can be used to bring the processor
out of LPSTOP. Optionally, the SIM can also continue to generate the CLKOUT signal
while in low-power stop mode.
STSIM and STEXT bits in SYNCR determine clock operation during low-power stop
mode.
The flowchart shown in Figure 5-5 summarizes the effects of the STSIM and STEXT
bits when the MCU enters normal low power stop mode. Any clock in the off state is
held low. If the synthesizer VCO is turned off during low-power stop mode, there is a
PLL relock delay after the VCO is turned back on.