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MC68336/376
SYSTEM INTEGRATION MODULE
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
5-41
5.7.3.1 Data Bus Mode Selection
All data lines have weak internal pull-up drivers. When pins are held high by the inter-
nal drivers, the MCU uses a default operating configuration. However, specific lines
can be held low externally during reset to achieve an alternate configuration.
NOTE
External bus loading can overcome the weak internal pull-up drivers
on data bus lines and hold pins low during reset.
Use an active device to hold data bus lines low. Data bus configuration logic must
release the bus before the first bus cycle after reset to prevent conflict with external
memory devices. The first bus cycle occurs ten CLKOUT cycles after RESET is
released. If external mode selection logic causes a conflict of this type, an isolation
resistor on the driven lines may be required. Figure 5-16 shows a recommended
method for conditioning the mode select signals.
The mode configuration drivers are conditioned with R/W and DS to prevent conflicts
between external devices and the MCU when reset is asserted. If external RESET is
asserted during an external write cycle, R/W conditioning (as shown in Figure 5-16)
prevents corruption of the data during the write. Similarly, DS conditions the mode con-
figuration drivers so that external reads are not corrupted when RESET is asserted
during an external read cycle.
Table 5-15 Reset Mode Selection
Mode Select Pin
Default Function
(Pin Left High)
Alternate Function
(Pin Pulled Low)
DATA0
CSBOOT 16-bit
CSBOOT 8-bit
DATA1
CS0
CS1
CS2
BR
BG
BGACK
DATA2
CS3
CS4
CS5
FC0
FC1
FC2
DATA3
DATA4
DATA5
DATA6
DATA7
CS6
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
ADDR19
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
DATA8
DSACK[1:0],
AVEC, DS, AS, SIZ[1:0]
PORTE
DATA9
IRQ[7:1]
MODCLK
PORTF
DATA11
Normal operation1
NOTES:
1. The DATA11 bus must remain high during reset to ensure normal operation.
Reserved
MODCLK
VCO = System clock
EXTAL = System clock
BKPT
Background mode disabled
Background mode enabled