MC68336/376
REGISTER SUMMARY
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
D-28
The SUPV bit designates the assignable space as supervisor or unrestricted.
0 = Only the module configuration register, test register, and interrupt register are
designated as supervisor-only data space. Access to all other locations is
unrestricted.
1 = All QADC registers and tables are designated as supervisor-only data space.
IARB[3:0] — Interrupt Arbitration ID
The IARB field is used to arbitrate between simultaneous interrupt requests of the
same priority. Each module that can generate interrupt requests must be assigned a
unique, non-zero IARB field value.
D.5.2 QADC Test Register
QADCTEST — QADC Test Register
$YFF202
Used for factory test only.
D.5.3 QADC Interrupt Register
IRLQ1[2:0] — Queue 1 Interrupt Level
When queue 1 generates an interrupt request, IRLQ1[2:0] determines which of the
interrupt request signals is asserted. When a request is acknowledged, the QADC
compares IRLQ1[2:0] to a mask value supplied by the CPU32 to determine whether to
respond. IRLQ1[2:0] must have a value in the range of $0 (interrupts disabled) to $7
(highest priority).
IRLQ2[2:0] — Queue 2 Interrupt Level
When queue 2 generates an interrupt request, IRLQ2[2:0] determines which of the
interrupt request signals is asserted. When a request is acknowledged, the QADC
compares IRLQ2[2:0] to a mask value supplied by the CPU32 to determine whether to
respond. IRLQ2[2:0] must have a value in the range of $0 (interrupts disabled) to $7
(highest priority).
IVB[7:0] — Interrupt Vector Base
Only the upper six bits of IVB[7:0] can be initialized. During interrupt arbitration, the
vector provided by the QADC is made up of IVB[7:2], plus two low-order bits that
identify one of the four QADC interrupt sources. Once IVB is written, the two low-order
bits always read as zeros.
QADCINT — QADC Interrupt Register
$YFF204
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
IRLQ1[2:0]
RSVD
IRLQ2[2:0]
IVB[7:2]
IVB[1:0]1
NOTES:
1. Bits 1 and 0 are supplied by the QADC.
RESET:
0
1