MC68336/376
SYSTEM INTEGRATION MODULE
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
5-63
5.10 Parallel Input/Output Ports
Sixteen SIM pins can be configured for general-purpose discrete input and output.
Although these pins are organized into two ports, port E and port F, function assign-
ment is by individual pin. Pin assignment registers, data direction registers, and data
registers are used to implement discrete I/O.
5.10.1 Pin Assignment Registers
Bits in the port E and port F pin assignment registers (PEPAR and PFPAR) control the
functions of the pins on each port. Any bit set to one defines the corresponding pin as
a bus control signal. Any bit cleared to zero defines the corresponding pin as an I/O
pin.
5.10.2 Data Direction Registers
Bits in the port E and port F data direction registers (DDRE and DDRF) control the
direction of the pin drivers when the pins are configured as I/O. Any bit in a register set
to one configures the corresponding pin as an output. Any bit in a register cleared to
zero configures the corresponding pin as an input. These registers can be read or
written at any time.
5.10.3 Data Registers
A write to the port E and port F data registers (PORTE[0:1] and PORTF[0:1]) is stored
in an internal data latch, and if any pin in the corresponding port is configured as an
output, the value stored for that bit is driven out on the pin. A read of a data register
returns the value at the pin only if the pin is configured as a discrete input. Otherwise,
the value read is the value stored in the port data register. Both data registers can be
accessed in two locations and can be read or written at any time.
Table 5-22 CSBOOT Base and Option Register Reset Values
Fields
Reset Values
Base address
$000000
Block size
1 Mbyte
Async/sync mode
Asynchronous mode
Upper/lower byte
Both bytes
Read/write
AS/DS
AS
DSACK
13 wait states
Address space
Supervisor/user space
IPL1
NOTES:
1. These fields are not used unless “Address space” is set to CPU space.
Any level
Autovector
Interrupt vector externally