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参数资料
| 型号： | SSTUG32868ET/G |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 锁存器 |
| 英文描述： | 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA176 |
| 封装： | 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176 |
| 文件页数： | 10/29页 |
| 文件大小： | 166K |
| 代理商： | SSTUG32868ET/G |
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SSTUG32868_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 23 April 2007
18 of 29
NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G congurable registered buffer with parity
[1]
This parameter is not necessarily production tested.
[2]
VREF must be held at a valid input voltage level, and data inputs must be held LOW for a minimum time of tACT(max) after RESET is
taken HIGH.
[3]
VREF, data and clock inputs must be held at valid voltage levels (not oating) a minimum time of tINACT(max) after RESET is taken LOW.
[1]
Includes 350 ps of test-load transmission line delay.
Table 9.
Timing requirements
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclk
clock frequency
-
450
MHz
tW
pulse duration
CK, CK HIGH or LOW
1
-
ns
tACT
differential inputs active
time
[1][2] -
-
10
ns
tINACT
differential inputs inactive
time
[1][3] -
-
15
ns
tsu
set-up time
DCSn before CK
↑, CK↓
0.6
-
ns
DODTn, DCKEn and Dn before CK
↑, CK↓
0.5
-
ns
PAR_IN before CK
↑, CK↓
0.5
-
ns
th
hold time
DCSn, DODTn, DCKEn and Dn after CK
↑, CK↓
0.4
-
ns
PAR_IN after CK
↑, CK↓
0.4
-
ns
Table 10.
Switching characteristics
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclk(max)
maximum clock frequency
input
450
-
MHz
tPDM
peak propagation delay
single bit switching;
from CK
↑ and CK↓ to Qn
[1] 1.0
-
1.4
ns
tPLH
LOW-to-HIGH propagation delay
from CK
↑ and CK↓ to QERR
1.2
-
3
ns
from RESET
↑ to QERR↓
--3
ns
tPHL
HIGH-to-LOW propagation delay
from CK
↑ and CK↓ to QERR
1
-
2.4
ns
from RESET
↑ to Qn↓
--3
ns
tPDMSS
simultaneous switching
peak propagation delay
from CK
↑ and CK↓ to Qn
[1] -
-
1.5
ns
Table 11.
Output edge rates
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
dV/dt_r
rising edge slew rate
from 20 % to 80 %
1
-
4
V/ns
dV/dt_f
falling edge slew rate
from 80 % to 20 %
1
-
4
V/ns
dV/dt_
absolute difference between dV/dt_r
and dV/dt_f
(from 20 % to 80 %) or
(from 80 % to 20 %)
-
1
V/ns
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SSTUG32868ETS | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications |
| SSTUG32868G | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications |
| SSTUH32864 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.8 V high output drive configurable registered buffer for DDR2 RDIMM applications |
| SSTUH32864EC | 功能描述:寄存器 1.8V CONFIG REG BUFFER/DDRII RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| SSTUH32864EC,518 | 功能描述:寄存器 1.8V CONFIG REG RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
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