参数资料
型号: SSTUG32868ET/G
厂商: NXP SEMICONDUCTORS
元件分类: 锁存器
英文描述: 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA176
封装: 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176
文件页数: 2/29页
文件大小: 166K
代理商: SSTUG32868ET/G
SSTUG32868_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 23 April 2007
10 of 29
NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G congurable registered buffer with parity
[1]
Data inputs = D1 to D5, D7, D9 to D12, D17 to D28 when C = 0.
Data inputs = D1 to D12, D17 to D20, D22, D24 to D28 when C = 1.
[2]
Data outputs = Q1x to Q5x, Q7x, Q9x to Q12x, Q17x to Q28x when C = 0.
Data outputs = Q1x to Q12x, Q17x to Q20x, Q22x, Q24x to Q28x when C = 1.
7.
Functional description
7.1 Function table
[1]
Q0 is the previous state of the associated output.
[2]
DCS2 and DCS3 operate identically to DCS0 and DCS1, except they do not have corresponding re-driven (QCS) outputs.
GND
A4, A6, C3, C4, C5, C6,
E3, E4, E5, E6, G3, G4,
G5, G6, J3, J4, J5, J6, L4,
L5, L6, N3, N4, N5, N6, R3,
R4, R5, R6, U3, U4, U5,
U6, W3, W4, W5, W6, AA3,
AA4, AA5, AA6
A4, A6, C3, C4, C5, C6,
E3, E4, E5, E6, G3, G4,
G5, G6, J3, J4, J5, J6, L4,
L5, L6, N3, N4, N5, N6, R3,
R4, R5, R6, U3, U4, U5,
U6, W3, W4, W5, W6, AA3,
AA4, AA5, AA6
ground
input
Ground.
SELDR
AB3
LVCMOS
input with
weak
pull-up
Selects output drive strength: ‘HIGH’ for
normal drive; ‘LOW’ for high drive. This
pin will default HIGH if left open-circuit
(built-in weak pull-up resistor).
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
1 : 2 Register A (C = 0)
1 : 2 Register B (C = 1)
Table 4.
Function table (each ip-op)
Inputs
RESET
CSGEN
CK
Dn, DODTn,
DCKEn
Qn
QCS0x QCS1x
QODTn,
QCKEn
HL
L
X
↑↓
LL
L
HL
L
X
↑↓
HH
L
H
L
X
L or H
X
Q0
HL
H
X
↑↓
LL
L
H
L
HL
H
X
↑↓
HH
L
H
L
H
X
L or H
X
Q0
HH
L
X
↑↓
LL
H
L
HH
L
X
↑↓
HH
H
L
H
L
X
L or H
X
Q0
HH
H
L
↑↓
LL
H
L
HH
H
L
↑↓
HH
H
L
L or H
X
Q0
HH
H
↑↓
LQ0
HH
L
HH
H
↑↓
HQ0
HH
H
L or H
X
Q0
L
X or
oating
X or
oating
X or oating
X or
oating
X or
oating
X or oating
L
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