参数资料
型号: SSTUG32868ET/G
厂商: NXP SEMICONDUCTORS
元件分类: 锁存器
英文描述: 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA176
封装: 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176
文件页数: 14/29页
文件大小: 166K
代理商: SSTUG32868ET/G
SSTUG32868_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 23 April 2007
21 of 29
NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G congurable registered buffer with parity
11.2 Data output slew rate measurement
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR
≤ 10 MHz; Z
0 =50 ; input slew rate = 1 V/ns ± 20 %, unless otherwise specied.
(1) CL includes probe and jig capacitance.
Fig 15. Load circuit, HIGH-to-LOW slew measurement
Fig 16. Voltage waveforms, HIGH-to-LOW slew rate measurement
(1) CL includes probe and jig capacitance.
Fig 17. Load circuit, LOW-to-HIGH slew measurement
Fig 18. Voltage waveforms, LOW-to-HIGH slew rate measurement
CL = 10 pF(1)
VDD
OUT
DUT
test point
RL = 50
002aaa377
VOH
VOL
output
80 %
20 %
dv_f
dt_f
002aaa378
CL = 10 pF(1)
OUT
DUT
test point
RL = 50
002aaa379
VOH
VOL
80 %
20 %
dv_r
dt_r
output
002aaa380
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