参数资料
型号: SSTUG32868ET/G
厂商: NXP SEMICONDUCTORS
元件分类: 锁存器
英文描述: 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA176
封装: 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176
文件页数: 7/29页
文件大小: 166K
代理商: SSTUG32868ET/G
SSTUG32868_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 23 April 2007
15 of 29
NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G congurable registered buffer with parity
(1) After RESET is switched from HIGH to LOW, all data and clock input signals must be held at valid logic levels (not oating)
for a minimum time of tINACT(max).
Fig 8.
Timing diagram during shutdown (RESET switches from HIGH to LOW)
CK(1)
CSGEN(1)
RESET
tINACT
tPHL
RESET to Q
PAR_IN(1)
tPLH
RESET to QERR
QERR
HIGH, LOW, or Don't care
HIGH or LOW
CK(1)
Dn, DODTn,
DCKEn(1)
Qn, QODTn,
QCKEn
002aac511
DCSn(1)
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SSTUG32868ETS 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications
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