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参数资料
型号： ST10F269DIETR
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, UUC
封装： DIE
文件页数： 40/161页
文件大小： 1595K
代理商： ST10F269DIETR
ST10F269-T3
134/160
21.3.1 - A/D Converter Characteristics
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, 4.0V ≤ VAREF ≤ VDD + 0.1V; VSS0.1V ≤ VAGND ≤ VSS + 0.2V
Notes: 1. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be
X000h or X3FFh, respectively.
2. During the tS sample time the input capacitance Cain can be charged/discharged by the external source. The internal resistance of
the analog source must allow the capacitance to reach its final voltage level within the tS sample time. After the end of the tS sample
time, changes of the analog input voltage have no effect on the conversion result. Values for the tSC sample clock depend on the
programming. Referring to the tC conversion time formula of Section 21.3.2 - on page 135 and to Table 33 on page 135:
- tS min = 2 tSC min = 2 tCC min = 2 x 24 x TCL = 48 TCL
- tS max = 2 tSC max = 2 x 8 tCC max = 2 x 8 x 96 TCL = 1536 TCL
TCL is defined in Section 21.4.2 -, Section 21.4.4 -, and Section 21.4.5 - on page 138:
3. The conversion time formula is:
- tC = 14 tCC + tS + 4 TCL (= 14 tCC + 2 tSC + 4 TCL)
The tC parameter includes the tS sample time, the time for determining the digital result and the time to load the result register with
the result of the conversion. Values for the tCC conversion clock depend on the programming. Referring to Table 33 on page 135:
- tC min = 14 tCC min + tS min + 4 TCL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL
- tC max = 14 tCC max + tS max + 4 TCL = 14 x 96 TCL + 1536 TCL + 4 TCL = 2884 TCL
4. This parameter is fixed by ADC control logic.
5. DNL, INL, TUE are tested at VAREF =5.0V, VAGND =0V, VCC = 4.9V. It is guaranteed by design characterization for all other
voltages within the defined voltage range.
‘LSB’ has a value of VAREF / 1024.
The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum 2 not selected analog input
pins and the absolute sum of input overload currents on all analog input pins does not exceed 10mA.
6. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channel with an
absolute overload current less than 10mA.
7. Partially tested, guaranteed by design characterization.
8.To remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be connected at
the ADC input. The cut-off frequency of this filter should avoid 2 opposite transitions during the ts sampling time of the ST10 ADC:
- fcut-off ≤ 1 / 5 ts to 1/10 ts
where ts is the sampling time of the ST10 ADC and is not related to the Nyquist frequency determined by the tc conversion time.
Table 32 : A/D Converter Characteristics
Symbol
Parameter
Test Condition
Limit Values
Unit
minimum
maximum
VAREF
SR
Analog Reference voltage
4.0
VDD + 0.1
V
VAIN
SR
Analog input voltage
1 - 8
VAGND
VAREF
V
IAREF
CC
Reference supply current
running mode
power-down mode
7
–
500
1
A
CAIN
CC
ADC input capacitance
Not sampling
Sampling
7
–
10
15
pF
tS
CC
Sample time
2 - 4
48 TCL
1 536 TCL
tC
CC
Conversion time
3 - 4
388 TCL
2 884 TCL
DNL
CC
Differential Nonlinearity
5
-0.5
+0.5
LSB
INL
CC
Integral Nonlinearity
5
-1.5
+1.5
LSB
OFS
CC
Offset Error
5
-1.0
+1.0
LSB
TUE
CC
Total unadjusted error
5
-2.0
+2.0
LSB
RASRC
SR
Internal resistance of analog source
tS in [ns]
2 - 7
–(tS / 150) - 0.25
k
K
CC
Coupling Factor between inputs
6 - 7
–
1/500
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