ST7MC1/ST7MC2
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MOTOR CONTROLLER (Cont’d)
Table 62. PWM mode when SR=1
Table 63. PWM mode when DAC=1
Warning: As the MCRB register contains preload
bits with, it has to be written as a complete byte. A
Bit Set or Bit Reset instruction on a non-preload bit
will have the effect of resetting all the preload bits.
CONTROL REGISTER C (MCRC)
Read/Write (except EDIR bit)
Reset Value: 0000 0000 (00h)
Bit 7= SEI/OI: Speed Error interrupt flag / MTIM
Overflow flag
Position Sensor or Sensorless mode (TES[1:0]
bits =00):
OI: MTIM Overflow flag
This flag signals an overflow of the MTIM timer. It
has to be cleared by software.
0: No MTIM timer overflow
1: MTIM timer overflow
Note: No interrupt is associated with this flag
Speed Sensor mode (TES[1:0] bits =01, 10, 11):
SEI: Speed error interrupt flag
0: No Tacho Error interrupt pending
1: Tacho Error interrupt pending
Bit 6= EDIR/HZ : Encoder Direction bit/ Hardware
zero-crossing event bit
Position Sensor or Sensorless mode (TES[1:0]
bits =00):
HZ: Hardware zero-crossing event bit
This Read/Write bit selects if the Z event is hard-
ware or not.
0: No hardware zero-crossing event
1: Hardware zero-crossing event
Speed Sensor mode (TES[1:0] bits =01, 10, 11):
EDIR:Encoder Direction bit
This bit is Read only. As the rotation direction de-
pends on encoder outputs and motor phase con-
nections, this bit cannot indicate absolute direc-
tion. It therefore gives the relative phase-shift (i.e.
advance/delay) between the two signals in quad-
rature output by the encoder (see
Figure 90).
0: MCIA input delayed compared to MCIB input.
1: MCIA input in advance compared to MCIB input
Bit 5 = SZ: Simulated zero-crossing event bit
0: No simulated zero-crossing event
1: Simulated zero-crossing event
Bit 4 = SC: Simulated commutation event bit
0: Hardware commutation event in auto-switched
mode (SWA = 1 in MCRA register)
1: Simulated commutation event in auto-switched
mode (SWA = 1 in MCRA register).
Bit 3 = SPLG: Sampling Z event at high frequency
in sensorless mode (SR=0)
This bit enables sampling at high frequency in sen-
sorless mode independently of the PWM signal or
only during ON time if the DS[3:0] bits in the
MCONF register contain a value. Refer to
0: Normal mode (Z sampling at PWM frequency at
the end of the off time)
1: Z event sampled at fSCF (see Table 82) Note: When the SPLG bit is set, there is no mini-
mum OFF time programmed by the OT [3:0] bits,
the OFF time is forced to 0s. This means that in
current mode, the OFF time of the PWM signal will
come only from the current loop.
OS2
bit
PWM after
C and
before Z
OS1
bit
Unused OS0
PWM after Z
and before
next C
0
On High
Channels
xx
0
On high
channels
1
On low
channels
1
On Low
Channels
xx
0
On high
channels
1
On low
channels
OS2
bit
Unused
OS1
bit
Unused OS0
PWM on
outputs
xx
x
0
On high
channels
1
On low
channels
7
6
5
43
21
0
SEI /
OI
EDIR/
HZ
SZ
SC
SPLG
VR2
VR1
VR0
1