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| 型号： | ST7PLITEUS5U3TR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, DSO8 |
| 封装： | LEAD FREE, DFN-8 |
| 文件页数： | 25/108页 |
| 文件大小： | 1957K |
| 代理商： | ST7PLITEUS5U3TR |
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ST7LITEUSx
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RESET SEQUENCE MANAGER (Cont’d)
6.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized (see Figure 13). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until VDD is over the minimum
level specified for the selected fCLKIN frequency.
A proper reset signal for a slow rising VDD supply
can generally be provided by an external RC net-
work connected to the RESET pin.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
The LVD filters spikes on VDD larger than tg(VDD) to
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 13.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 13. RESET Sequences
VDD
RUN
RESET PIN
EXTERNAL
WATCHDOG
ACTIVE PHASE
VIT+(LVD)
VIT-(LVD)
th(RSTL)in
RUN
WATCHDOG UNDERFLOW
tw(RSTL)out
RUN
RESET
SOURCE
EXTERNAL
RESET
LVD
RESET
WATCHDOG
RESET
INTERNAL RESET (64 TCPU)
VECTOR FETCH
ACTIVE
PHASE
ACTIVE
PHASE
1
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