参数资料
型号: ST7PLITEUS5U3TR
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, DSO8
封装: LEAD FREE, DFN-8
文件页数: 33/108页
文件大小: 1957K
代理商: ST7PLITEUS5U3TR
ST7LITEUSx
30/108
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
Figure 17. Using the AVD to Monitor VDD
7.4.3 Low Power Modes
7.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding Enable Control Bit (AVDIE) is
set and the interrupt mask in the CC register is re-
set (RIM instruction).
VDD
VIT+(AVD)
VIT-(AVD)
AVDF bit
01
RESET
IF AVDIE bit = 1
Vhyst
AVD INTERRUPT
REQUEST
INTERRUPT Cleared by
VIT+(LVD)
VIT-(LVD)
LVD RESET
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
0
1
hardware
INTERRUPT Cleared by
reset
Mode
Description
WAIT
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
HALT
The SICSR register is frozen.
The AVD remains active but the AVD inter-
rupt cannot be used to exit from Halt mode.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
AVD event
AVDF
AVDIE
Yes
No
1
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