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参数资料
型号： ST7PLITEUS5U3TR
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, DSO8
封装： LEAD FREE, DFN-8
文件页数： 34/108页
文件大小： 1957K
代理商： ST7PLITEUS5U3TR
ST7LITEUSx
31/108
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.4.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS
REGISTER (SICSR)
Read/Write
Reset Value: 0000 0x00 (0xh)
Bit 7 = Reserved, must be kept cleared.
Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-
justment bits
These bits, as well as CR[9:2] bits in the RCCR
register must be written immediately after reset to
adjust the RC oscillator frequency and to obtain
the required accuracy. Refer to section 6.1 on
page 17.
Bits 4:3 = Reserved, must be kept cleared.
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared when read. See WDGRF flag de-
scription in Section 10.1 for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Note:
If the selected clock source is one of the two inter-
nal ones, and if VDD remains below the selected
LVD threshold during less than TAWU (33us typ.),
the LVDRF flag cannot be set even if the device is
reset by the LVD.
If the selected clock source is the external clock
(CLKIN), the flag is never set if the reset occurs
during Halt mode. In run mode the flag is set only
if fCLKIN is greater than 10MHz.
Bit 1 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit is set. Refer to Figure
17 for additional details
0: VDD over AVD threshold
1: VDD under AVD threshold
Bit 0 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag is
set. The pending interrupt information is automati-
cally cleared when software enters the AVD inter-
rupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
AVD THRESHOLD SELECTION REGISTER
(AVDTHCR)
Read/Write
Reset Value: 0000 0011 (03h)
Bit 7 = Reserved, must be kept cleared.
Bits 6:5 = CK[1:0] internal RC Prescaler Selection
Refer to Section 6.1 INTERNAL RC OSCILLATOR
ADJUSTMENT on page 17.
Bits 4:2 = Reserved, must be kept cleared.
Bits 1:0 = AVD[1:0] AVD Threshold Selection
These bits are set and cleared by software and set
by hardware after a reset. They select the AVD
threshold.
Table 9. AVD Threshold Selection bits
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
70
0
CR1 CR0
0
LVDRF AVDF AVDIE
70
0
CK1 CK0
0
AVD1 AVD0
AVD1 AVD0
Functionality
0
Low
0
1
Medium
10
High
1
AVD off
1
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