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参数资料
| 型号： | ST7PLITEUS5U3TR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, DSO8 |
| 封装： | LEAD FREE, DFN-8 |
| 文件页数： | 39/108页 |
| 文件大小： | 1957K |
| 代理商： | ST7PLITEUS5U3TR |
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POWER SAVING MODES (Cont’d)
8.4.2 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when active halt mode is disa-
bled.
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 7, “Interrupt
Mapping,” on page 26) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the main oscillator is immediately turned on and
the 64 CPU cycle delay is used to stabilize it. After
the start up delay, the CPU resumes operation by
servicing the interrupt or by fetching the reset vec-
tor which woke it up (see Figure 24).
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see sec-
tion 14.1 on page 95 for more details).
Figure 23. HALT Timing Overview
Note:
1. A reset pulse of at least 42s must be applied
when exiting from HALT mode.
Figure 24. HALT Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 7, “Interrupt Mapping,” on page 26 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
5. The CPU clock must be switched to 1MHz
(RC/8) or AWU RC before entering HALT mode.
HALT
RUN
64 CPU CYCLE
DELAY
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
[Active Halt disabled]
HALT INSTRUCTION
RESET
INTERRUPT 3)
Y
N
Y
CPU
OSCILLATOR
PERIPHERALS 2)
IBIT
OFF
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
OFF
X 4)
ON
CPU
OSCILLATOR
PERIPHERALS
IBITS
ON
X 4)
ON
64 CPU CLOCK CYCLE
DELAY 5)
WATCHDOG
ENABLE
DISABLE
WDGHALT 1)
0
WATCHDOG
RESET
1
(Active Halt disabled)
1
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