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参数资料
| 型号： | ST7PLITEUS5U3TR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, DSO8 |
| 封装： | LEAD FREE, DFN-8 |
| 文件页数： | 77/108页 |
| 文件大小： | 1957K |
| 代理商： | ST7PLITEUS5U3TR |
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12.3.2 Operating Conditions with Low Voltage Detector (LVD)
TA = -40 to 125°C, unless otherwise specified
Notes:
1. Not tested in production.
2. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on and LVD reset
release. When the VDD slope is outside these values, the LVD may not release properly the reset of the MCU.
3. LVD and AVD high thresholds must not be selected at the same time.
4. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is
recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 62 on page
87.
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds
TA = -40 to 125°C, unless otherwise specified
Notes:
1. LVD and AVD high thresholds must not be selected at the same time.
2. Not tested in production, guaranteed by characterization.
Note: Refer to section 7.4.2.1 on page 29
Symbol
Parameter
Conditions 3)
Min
Typ
Max
Unit
VIT+(LVD)
Reset release threshold
(VDD rise)
High Threshold
Med. Threshold
Low Threshold
3.50
3.30
2.50
4.00
3.70
2.65
4.50
4.30
3.30
V
VIT-(LVD)
Reset generation threshold
(VDD fall)
High Threshold
Med. Threshold
Low Threshold
3.30
3.20
2.40
3.80
3.50
2.70
4.40
4.20
3.20
Vhys
LVD voltage threshold hysteresis
VIT+(LVD)-VIT-(LVD)
150
mV
VtPOR
VDD rise time rate
2) 4)
20
-
s/V
IDD(LVD)
1)
LVD/AVD current consumption
VDD = 5V
220
A
Symbol
Parameter
Conditions 1)
Min 2)
Typ 2)
Max 2)
Unit
VIT+(AVD)
1=>0 AVDF flag toggle threshold
(VDD rise)
High Threshold
Med. Threshold
Low Threshold
3.50
3.30
2.50
4.10
3.90
3.00
4.80
4.60
3.50
V
VIT-(AVD)
0=>1 AVDF flag toggle threshold
(VDD fall)
High Threshold
Med. Threshold
Low Threshold
3.40
3.20
2.40
4.00
3.80
2.90
4.70
4.50
3.40
Vhys
AVD voltage threshold hysteresis
VIT+(AVD)-VIT-(AVD)
100
mV
V
IT-
Voltage drop between AVD flag set
and LVD reset activation
VDD fall
0.45
V
1
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