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参数资料
| 型号： | TLC320AC02IPM |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封装： | GREEN, PLASTIC, QFP-64 |
| 文件页数： | 20/86页 |
| 文件大小： | 471K |
| 代理商： | TLC320AC02IPM |
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2–13
2.14.5
Midpoint Voltages (ADC VMID and DAC VMID)
Since the device operates at a single-supply voltage, two midpoint voltages are generated for internal signal
processing. ADC VMID is used for the ADC channel reference, and DAC VMID is used for the DAC channel
reference. Two references minimize channel-to-channel noise and crosstalk. ADC VMID and DAC VMID
must be buffered when used as a reference for external signal processing.
2.15 Device Functions
2.15.1
Phase Adjustment
In some applications, such as modems, the device sampling period may require an adjustment to
synchronize with the incoming bit stream to improve the signal-to-noise ratio. The TLC320AC02 can adjust
the sampling period through the use of the A
′ register and the control bits.
2.15.1.1 Phase-Adjustment Control
A phase adjustment is a programmed variation in the sampling period. A sampling period is adjusted
according to the data value in the A
′ register, and the phase adjustment is that number of master clocks
(MCLK). An adjustment is made during device operation with data bits D01 and D00 in the primary
communication, with data bits DS15 and DS14 in the secondary word or in combination with the hardware
terminals FC1 and FC0 (see Table 2 – 3). This adjustment request is latched on the rising edge of the next
internal frame-sync interval and is only valid for the next sampling period. To repeat the phase adjustment,
another phase request must be initiated.
2.15.1.2 Use of the A
′ Register for Phase Adjustment
The A
′ register value makes slight timing adjustments to the sampling period. The sampling period
increases or decreases according to the sign of the programmed A
′ register value and the state of data bits
D01 and D00 in the primary data word.
The general equation for the conversion frequency is given in equation 16:
+
MCLK
(2
A register value
B register value)
" (A register value)
fs = conversion frequency
(16)
Therefore, if A
′ = 0, the device conversion (sampling) frequency and period is constant.
If a nonzero A
′ value is programmed, the sampling frequency and period responds as shown in Table 2–2.
Table 2–2. Sampling Variation With A
′
SIGN OF THE A
′ REGISTER VALUE
D01
D00
PLUS VALUE
(+)
NEGATIVE VALUE
(–)
0
1
(increase command)
Frequency decreases,
period increases
Frequency increases,
period decreases
1
0
(decrease command)
Frequency increases,
period decreases
Frequency decreases,
period increases
An adjustment to the sampling period, which must be requested through D01 and D00 of the primary data
word to DIN, is valid for the following sampling period only. When the adjustment is required for the
subsequent sampling period, it must be requested again through D01 and D00 of the primary data word.
For each request, only the sampling period occurring immediately after the primary data word request is
affected.
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