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| 型号： | TLC320AC02IPM |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封装： | GREEN, PLASTIC, QFP-64 |
| 文件页数： | 6/86页 |
| 文件大小： | 471K |
| 代理商： | TLC320AC02IPM |
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1–8
1.5
Register Functional Summary
There are nine data registers that are used as follows:
Register 0
The No-op register. The 0 address allows phase adjustments to be made without
reprogramming a data register.
Register 1
The A register controls the count of the A counter.
Register 2
The B register controls the count of the B counter.
Register 3
The A
′ register controls the phase adjustment of the sampling period. The adjustment is
equal to the register value multiplied by the input master period.
Register 4
The amplifier gain register controls the gains of the input, output, and monitor amplifiers.
Register 5
The analog configuration register controls:
The addition/deletion of the high-pass filter to the ADC signal path
The enable/disable of the analog loopback
The selection of the regular inputs or auxiliary inputs
The function that allows processing of signals that are the sum of the regular inputs and
the auxiliary inputs (VIN + VAUX IN)
Register 6
The digital configuration register controls:
Selection of the free-run function
FSD [frame-synchronization (sync) delay] output enable/disable
Selection of 16-bit function
Forcing secondary communications
Software reset
Software power down
Register 7
The frame-sync delay register controls the time delay between the master-device frame
sync and slave-device frame sync. Register 7 must be the last register programmed when
using slave devices since all register data is latched and valid on the sixteenth falling edge
of SCLK. On the sixteenth falling edge of SCLK, all delayed frame-sync intervals are shifted
by this programmed amount.
Register 8
The frame-sync number register informs the master device of the number of slaves that are
connected in the chain. The frame-sync number is equal to the number of slaves plus one.
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