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参数资料
| 型号： | TLC320AC02IPM |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封装： | GREEN, PLASTIC, QFP-64 |
| 文件页数： | 21/86页 |
| 文件大小： | 471K |
| 代理商： | TLC320AC02IPM |
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2–14
The amount of time shift in the entire sampling period (1/fs) is as follows:
When the sampling period is set to 125
s (8 kHz), the A′ register is loaded with decimal 10 and the
TLC320AC02 master clock frequency is 10.386 MHz. The amount of time each sampling period is increased
or decreased, when requested, is given in equation 17:
Time shift = (A
′ register value) × (MCLK period)
(17)
The device changes the entire sampling period by only the MCLK period times the A
′ register value as given
in equation 18:
Change in sampling period = contents of A
′ register × master clock period
= 10
× 96.45 ns = 964 ns (less than 1% of the sampling period)
(18)
The sampling period changes by 964.5 ns each time the phase adjustment is requested by the primary data
word (i.e., once per sampling period).
It is evident then that the change in sampling period is very small compared to the sampling period. To
observe this effect over a long period of time ( > sampling period), this change must be continuously
requested by the primary data word. If the adjustment is not requested again, the sampling period changes
only once and it may appear that there was no execution of the command. This is especially true when bench
testing the device. Automatic test equipment can test for results within a single sampling period.
Internally, the A
′ register value only affects one cycle (period) of the A counter. The A and A′ values are
additive, but only for one A-counter period. The A counter begins the first count at the default or programmed
A-register value and counts down to the A
′-register value. As the A′ value increases or decreases, the first
clock cycle from the A counter is lengthened or shortened. The initial A-counter period is the only counter
period affected by the A
′ register such that only this single period is increased or decreased.
2.15.2
Analog Loopback
This function allows the circuit to be tested remotely. In loopback, OUT+ and OUT– are internally connected
to IN + and IN –. The DAC data bits D15 to D02 that are applied to DIN can be compared with the ADC output
data bits D15 to D02 at DOUT. There are some differences due to the ADC and DAC channel offset. The
loopback function is implemented by setting DS01 and DS00 to zero in control register 5 (see Section 2.19).
When analog loopback is enabled, the external inputs to IN+ and IN– are disconnected, but the signals at
OUT+ and OUT– may still be read.
2.15.3
16-Bit Mode
In the 16-bit mode, the device ignores the last two control bits (D01 and D00) of the primary word and
requests continual secondary communications to occur. By ignoring the last two primary communication
bits, compatibility with existing 16-bit software can be maintained. This function is implemented by setting
bit DS03 to 1 in register 6. To return to normal operation, DS03 must be reprogrammed to 0.
2.15.4
Free-Run Mode
With the free-run bit set in register 6, the external shift clock and frame sync control only the data transfer.
The ADC and DAC timing are controlled by the A and B register values, and the phase-shift adjustment must
be done as if the device is in stand-alone mode (by the software or the state of FC1 and FC0).
Phase adjustment cannot be made by adjustment of the frame-sync timing. The external frame sync must
occur within 1/2 FCLK period of the internal frame sync (FCLK as determined by the values of the A and
B registers).
When the external frame sync occurs simultaneously with the internal load, the data-transfer request by the
external frame sync takes precedence over an internal load command. The latching of the ADC conversion
data in the output register is inhibited until the current 16 bits are shifted out of the register by the shift clock.
2.15.5
Force Secondary Communication
With bit 2 in register 6 set to 1, secondary communication is requested continuously. It overrides all software
and hardware requests concerning secondary communication. Phase shifting, however, can still be
performed with the software and hardware.
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