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参数资料
| 型号： | TLC320AC02IPM |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封装： | GREEN, PLASTIC, QFP-64 |
| 文件页数： | 4/86页 |
| 文件大小： | 471K |
| 代理商： | TLC320AC02IPM |
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1–6
1.4
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
OUT+
3
43
O
Noninverting output of analog output power amplifier. OUT+ can drive transformer
hybrids or high-impedance loads directly in a differential connection or a
single-ended configuration with a buffered VMID.
OUT–
4
46
O
Inverting output of analog output power amplifier. OUT– is functionally identical
with and complementary to OUT+.
PWR DWN
2
42
I
Power-down input. When PWR DWN is taken low, the device is powered down
such that the existing internally programmed state is maintained. When PWR
DWN is brought high, full operation resumes.
RESET
8
57
I
Reset input that initializes the internal counters and control registers. RESET
initiates the serial data communications, initializes all of the registers to their
default values, and puts the device in a preprogrammed state. After a low-going
pulse on RESET, the device registers are initialized to provide a 16-kHz
data-conversion rate and 7.2-kHz filter bandwidth for a 10.368-MHz master clock
input signal.
SCLK
13
8
I/O
Shift clock. SCLK clocks the digital data into DIN and out of DOUT during the
frame-synchronization interval. When configured as an output (M/S high), SCLK
is generated internally by dividing the master clock signal frequency by four. When
configured as an input (M/S low), SCLK is generated externally and
synchronously to the master clock. This signal clocks the serial data into and out
of the device.
SUBS
21
24
I
Substrate connection. SUBS should be tied to ADC GND.
Terminal numbers shown are for the FN package.
Terminal numbers shown are for the PM package.
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