
16.11 Transmit/Receive Operation
16.11.1
Data transmit operation
Set UART0CR1<TXE> to "1". Check UART0SR<TBFL> = "0", and then write data into TD0BUF (transmit
data buffer). Writing data into TD0BUF sets UART0SR<TBFL> to "1", transfers the data to the transmit shift
register, and outputs the data sequentially from the TXD0 pin. The data output includes a start bit, stop bits whose
number is specified in UART0CR1<STBT> and a parity bit if parity addition is specified. Select the data transfer
baud rate using UART0CR1<BRG>, UART0CR2<RTSEL> and UART0DR. When data transmission starts, the
transmit buffer full flag UART0SR<TBFL> is cleared to "0" and an INTTXD0 interrupt request is generated.
Note 1: After data is written into TD0BUF, if new data is written into TD0BUF before the previous data is transferred
to the shift register, the new data is written over the previous data and is transferred to the shift register.
Note 2: Under the conditions shown in
Table 16-9, the TXD0 pin output is fixed at the L or H level according to the
setting of UART0CR1<IRDASEL>.
Table 16-9 TXD0 Pin Output
Condition
TXD0 pin output
IRDASEL="0"
IRDASEL="1"
When UART0CR1<TXE> is "0"
H level
L level
From when "1" is written to
UART0CR1<TXE> to when the trans-
mitted data is written to TD0BUF
When the STOP, IDLE0 or SLEEP0
mode is active
16.11.2
Data receive operation
Set UART0CR1<RXE> to "1". When data is received via the RXD0 pin, the received data is transferred to
RD0BUF (receive data buffer). At this time, the transmitted data includes a start bit, stop bit(s) and a parity bit
if parity addition is specified. When the stop bit(s) are received, data only is extracted and transferred to RD0BUF
(receive data buffer). Then the receive buffer full flag UART0SR<RBFL> is set and an INTRXD0 interrupt
request is generated. Set the data transfer baud rate using UART0CR1<BRG>, UART0CR2<RTSEL> and
UART0DR.
If an overrun error occurs when data is received, the data is not transferred to RD0BUF (receive data buffer)
but discarded; data in the RD0BUF is not affected.
TMP89FH42
16. Asynchronous Serial Interface (UART)
16.11 Transmit/Receive Operation
Page 238
RA001