
I2C bus address register
I2C0AR
(0x0024)
7
6
5
4
3
2
1
0
Bit Symbol
SA
ALS
Read/Write
R/W
After reset
0
Note 1: Don't set I2C0AR<SA> to "0x00". If it is set to "0x00", the slave address is deemed to be matched when the I2C bus
standard start byte ("0x01") is received in the slave mode.
Note 2: Don't change the contents of the registers when the start condition is generated, the stop condition is generated or the
data transfer is in progress. Write data to the registers before the start condition is generated or during the period from
when an interrupt request is generated for stopping the data transfer until it is released.
Note 3: After a software reset is generated, all the bits of the SBI0CR2 register except SBI0CR2<SBIM> and the SBI0CR1, I2C0AR
and SBI0SR2 registers are initialized.
Note 4: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and
the SBI0CR1, I2C0AR and SBI0DBR registers are initialized.
Serial bus interface data buffer register
SBI0DBR
(0x0025)
7
6
5
4
3
2
1
0
Bit Symbol
SBI0DBR
Read/Write
R/W
After reset
0
Note 1: Write the transmit data beginning with the most significant bit (bit 7).
Note 2: SBI0DBR has individual writing and reading buffers, and written data cannot be read out. Therefore, SBI0DBR must not
be accessed by using a read-modify-write instruction, such as a bit operation.
Note 3: Don't change the contents of the registers when the start condition is generated, the stop condition is generated or the
data transfer is in progress. Write data to the registers before the start condition is generated or during the period from
when an interrupt request is generated for stopping the data transfer until it is released.
Note 4: To set SBI0CR2<PIN> to "1" by writing the dummy data to SBI0DBR, write 0x00. Writing any data other than 0x00 causes
an improper value in the subsequently received data.
Note 5: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and
the SBI0CR1, I2C0AR and SBI0DBR registers are initialized.
TMP89FH42
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