
External interrupt control register 3
EINTCR3
(0x0FDA)
7
6
5
4
3
2
1
0
Bit Symbol
-
INT3LVL
INT3ES
INT3NC
Read/Write
R
R/W
After reset
0
INI3LVL
Noise canceller pass signal level
when the interrupt request signal is
generated for external interrupt 3
0 :
1 :
Initial state or signal level "L"
Signal level "H"
INT3ES
Selects the interrupt request gener-
ating condition for external interrupt
3
00 : An interrupt request is generated at the rising edge of the noise canceller
pass signal
01 : An interrupt request is generated at the falling edge of the noise canceller
pass signal
10 : An interrupt request is generated at both edges of the noise canceller pass
signal
11 : Reserved
INT3NC
Sets the noise canceller sampling in-
terval for external interrupt 3
NORMAL1/2, IDLE1/2
SLOW1/2, SLEEP1
00 :
01 :
10 :
11 :
fcgck [Hz]
fcgck / 22 [Hz]
fcgck / 23 [Hz]
fcgck / 24 [Hz]
00 :
01 :
10 :
11 :
fs/4 [Hz]
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear
the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is
changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and
clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2,
wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
Note 3: Interrupt requests may be generated when EINTCR3 is changed. Before doing such operation, clear the corresponding
interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NOR-
MAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt
latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/
fspl [s] after the operation mode is changed and clear the interrupt latch.
Note 4: Bits 7 to 5 of EINTCR3 are read as "0".
TMP89FH42
4. External Interrupt control circuit
4.2 Control
Page 66
RA000