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参数资料
型号： TRK-MPC5634M
厂商： Freescale Semiconductor
文件页数： 1/122页
文件大小： 0K
描述： TRAK 5634M 144PN R2.1
设计资源： TRK-MPC5634M Schematic
标准包装： 1
系列： MPC56xx
类型： MCU
适用于相关产品： MPC5634M
所含物品： 板，线缆，CD，DVD
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5634M
Rev. 9, 05/2012
Freescale Semiconductor, Inc., 2008-2012. All rights reserved.
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
MPC5634M
208 MAPBGA
17 mm x 17 mm
144 LQFP
20 mm x 20 mm
176 LQFP
24 mm x 24 mm
Operating Parameters
— Fully static operation, 0 MHz – 80 MHz (plus
2% frequency modulation - 82 MHz)
— –40
C to 150 C junction temperature
operating range
— Low power design
– Less than 400 mW power dissipation
(nominal)
– Designed for dynamic power management
of core and peripherals
– Software controlled clock gating of
peripherals
– Low power stop mode, with all clocks
stopped
— Fabricated in 90 nm process
— 1.2 V internal logic
— Single power supply with
5.0 V
5% (4.5 V to 5.25 V) with
internal regulator to provide 3.3 V and 1.2 V for
the core
— Input and output pins with
5.0 V
5% (4.5 V to 5.25 V) range
– 35%/65% VDDE CMOS switch levels (with
hysteresis)
– Selectable hysteresis
– Selectable slew rate control
— Nexus pins powered by 3.3 V supply
— Designed with EMI reduction techniques
– Phase-locked loop
– Frequency modulation of system clock
frequency
– On-chip bypass capacitance
– Selectable slew rate and drive strength
High performance e200z335 core processor
— 32-bit Power Architecture Book E
programmer’s model
— Variable Length Encoding Enhancements
– Allows Power Architecture instruction set to
be optionally encoded in a mixed 16 and
32-bit instructions
– Results in smaller code size
— Single issue, 32-bit Power Architecture
technology compliant CPU
— In-order execution and retirement
— Precise exception handling
— Branch processing unit
– Dedicated branch address calculation adder
– Branch acceleration using Branch
Lookahead Instruction Buffer
— Load/store unit
– One-cycle load latency
– Fully pipelined
– Big and Little Endian support
– Misaligned access support
– Zero load-to-use pipeline bubbles
— Thirty-two 64-bit general purpose registers
(GPRs)
— Memory management unit (MMU) with
16-entry fully-associative translation look-aside
buffer (TLB)
— Separate instruction bus and load/store bus
— Vectored interrupt support
— Interrupt latency < 120 ns @ 80 MHz
(measured from interrupt request to execution of
first instruction of interrupt exception handler)
MPC5634M Microcontroller
Data Sheet
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