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| 型号： | TRK-MPC5634M |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 67/122页 |
| 文件大小： | 0K |
| 描述： | TRAK 5634M 144PN R2.1 |
| 设计资源： | TRK-MPC5634M Schematic |
| 标准包装： | 1 |
| 系列： | MPC56xx |
| 类型： | MCU |
| 适用于相关产品： | MPC5634M |
| 所含物品： | 板，线缆，CD，DVD |
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9 The GPIO functions on GPIO[206] and GPIO[207] can be selected as trigger functions in the SIU for the ADC by making the proper selections in the
SIU_ETISR and SIU_ISEL3 registers in the SIU.
10 Some signals in this section are available only on calibration package.
11 These pins are only available in the 496 CSP/MAPBGA calibration/development package.
12 On the calibration package, the Nexus function on this pin is enabled when the NEXUSCFG pin is high and Nexus is configured to full port mode. On the
176-pin and 208-pin packages, the Nexus function on this pin is enabled permanently. Do not connect the Nexus MDO or MSEO pins directly to a power
supply or ground.
13 In the calibration package, the I/O segment containing this pin is called VDDE12.
14 208-ball BGA package only
15 When configured as Nexus (208-pin package or calibration package with NEXUSCFG=1), and JCOMP is asserted during reset, MDO[0] is driven high until
the crystal oscillator becomes stable, at which time it is then negated.
16 The function of this pin is Nexus when NEXUSCFG is high.
17 High when the pin is configured to Nexus, low otherwise.
18 O/Low for the calibration with NEXUSCFG=0; I/Up otherwise.
19 ALT_ADDR/Low for the calibration package with NEXUSCFG=0; EVTI/Up otherwise.
20 In 176-pin and 208-pin packages, the Nexus function is disabled and the pin/ball has the secondary function
21 This signal is not available in the 176-pin and 208-pin packages.
22 The primary function is not selected via the PA field when the pin is a Nexus signal. Instead, it is activated by the Nexus controller.
23 TDI and TDO are required for JTAG operation.
24 The primary function is not selected via the PA field when the pin is a JTAG signal. Instead, it is activated by the JTAG controller.
25 The function and state of the CAN_A and eSCI_A pins after execution of the BAM program is determined by the BOOTCFG1 pin.
26 Connect an external 10K pull-up resistor to the SCI_A_RX pin to ensure that the pin is driven high during CAN serial boot.
27 For pins AN[0:7], during and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors
are disabled when the system clock propagates through the device.
28 ETPUA[24:29] are input and output. The input muxing is controlled by SIU_ISEL8 register.
29 eTPU_A[25] is an output only function.
30 Only the output channels of eTPU[8:9] are connected to pins.
31 The function after reset of the XTAL pin is determined by the value of the signal on the PLLCFG[1] pin. When bypass mode is chosen XTAL has no function
and should be grounded.
32 The function after reset of the EXTAL_EXTCLK pin is determined by the value of the signal on the PLLCFG[1] pin. If the EXTCLK function is chosen, the valid
operating voltage for the pin is 1.62 V to 3.6 V. If the EXTAL function is chosen, the valid operating voltage is 3.3 V.
33 VSSPLL and VSSREG are connected to the same pin.
34 This pin is shared by two pads: VDDA_AN, using pad_vdde_hv, and VDDA_DIG, using pad_vdde_int_hv.
35 This pin is shared by two pads: VSSA_AN, using pad_vsse_hv, and VSSA_DIG, using pad_vsse_int_hv.
36 VDDEH1A, VDDEH1B, and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support legacy
naming, however they should be considered as the same signal in this document.
37 LVDS pins will not work at 3.3 V.
38 The VDDEH6 segment may be powered from 3.0 V to 5.0 V for mux address or SSI functions, but must meet the VDDA specifications of 4.5 V to 5.25 V for
analog input function.
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