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| 型号： | TRK-MPC5634M |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 102/122页 |
| 文件大小： | 0K |
| 描述： | TRAK 5634M 144PN R2.1 |
| 设计资源： | TRK-MPC5634M Schematic |
| 标准包装： | 1 |
| 系列： | MPC56xx |
| 类型： | MCU |
| 适用于相关产品： | MPC5634M |
| 所含物品： | 板，线缆，CD，DVD |
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MPC5634M Microcontroller Data Sheet, Rev. 9
Electrical characteristics
Freescale Semiconductor
80
VILEXT
CC
T EXTAL input low voltage
Crystal Mode14,
0.65
Vxtal1.25V15
—Vxtal –
0.4
V
T
External Reference14,
0VRC33/2
– 0.4
—
CC
T XTAL load capacitance12
4MHz
5
30
pF
8MHz
5
26
12 MHz
5
23
16 MHz
5
19
20 MHz
5
16
tlpll
CC
P PLL lock time 12, 17
—
200
s
tdc
CC
T Duty cycle of reference
—40
60
%
fLCK
CC
T Frequency LOCK range
—
–6
6
% fsys
fUL
CC
T Frequency un-LOCK range
—
–18
18
% fsys
fCS
fDS
CC
D Modulation Depth
Center spread
±0.25
±4.0
%fsys
D
Down Spread
–0.5
–8.0
fMOD
CC
D Modulation frequency18
—
100
kHz
1 All values given are initial design targets and subject to change.
2 Considering operation with PLL not bypassed.
3 fVCO is calculated as follows:
— In Legacy Mode fVCO =(fcrystal / (PREDIV + 1)) * (4 * (MFD + 4))
— In Enhanced Mode fvco = (fcrystal / (EPREDIV + 1)) * (EMFD + 4)
4 All internal registers retain data at 0 Hz.
5 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked
mode.
6 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the
fLOR window.
7 fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in
enhanced mode.
8 This value is determined by the crystal manufacturer and board design.
9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the
CJITTER percentage for a given interval.
10 Proper PC board layout procedures must be followed to achieve specifications.
11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
12 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for
this PLL, load capacitors should not exceed these limits. For a 20 MHz crystal the maximum load should be 17 pF.
13 Proper PC board layout procedures must be followed to achieve specifications.
14 This parameter is guaranteed by design rather than 100% tested.
Table 27. PLLMRFM electrical specifications1
(VDDPLL =1.14 V to 1.32 V, VSS = VSSPLL = 0 V, TA = TL to TH) (continued)
Symbol
C
Parameter
Conditions
Value
Unit
min
max
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