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| 型号： | TRK-MPC5634M |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 36/122页 |
| 文件大小： | 0K |
| 描述： | TRAK 5634M 144PN R2.1 |
| 设计资源： | TRK-MPC5634M Schematic |
| 标准包装： | 1 |
| 系列： | MPC56xx |
| 类型： | MCU |
| 适用于相关产品： | MPC5634M |
| 所含物品： | 板，线缆，CD，DVD |
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MPC5634M Microcontroller Data Sheet, Rev. 9
Overview
Freescale Semiconductor
20
— Queue_0 can bypass all prioritization, buffering and abort current conversions to start a Queue_0 conversion a
deterministic time after the queue trigger
— Streaming mode operation of Queue_0 to execute some commands several times
— Supports software and hardware trigger modes to arm a particular Queue
— Generates interrupt when command coherency is not achieved
External hardware triggers
— Supports rising edge, falling edge, high level and low level triggers
— Supports configurable digital filter
Supports four external 8-to-1 muxes which can expand the input channels to 56 channels total
2.2.15
DSPI
The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the
MPC5634M MCU and external devices. The DSPI supports pin count reduction through serialization and deserialization of
eTPU and eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like
protocol. This SPI-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion,
etc. Each bit in the frame may be configured to serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI
can be configured to serialize data to an external device that supports the Microsecond Channel protocol. There are two identical
DSPI blocks on the MPC5634M MCU. The DSPI output pins support 5 V logic levels or Low Voltage Differential Signalling
(LVDS) according to the Microsecond Channel specification.
The DSPIs have three configurations:
Serial peripheral interface (SPI) configuration where the DSPI operates as an up to 16-bit SPI with support for queues
Enhanced deserial serial interface (DSI) configuration where DSPI serializes up to 32 bits with three possible sources
per bit
— eTPU, eMIOS, new virtual GPIO registers as possible bit source
— Programmable inter-frame gap in continuous mode
— Bit source selection allows microsecond channel downstream with command or data frames up to 32 bits
— Microsecond channel dual receiver mode
Combined serial interface (CSI) configuration where the DSPI operates in both SPI and DSI configurations
interleaving DSI frames with SPI frames, giving priority to SPI frames
For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers between the memory and
the DSPI FIFOs are accomplished through the use of the eDMA controller or through host software.
The DSPI supports these SPI features:
Full-duplex, synchronous transfers
Selectable LVDS Pads working at 40 MHz for SOUT and SCK pins
Master and Slave Mode
Buffered transmit operation using the TX FIFO with parameterized depth of 4 entries
Buffered receive operation using the RX FIFO with parameterized depth of 4 entries
TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues
Visibility into the TX and RX FIFOs for ease of debugging
FIFO Bypass Mode for low-latency updates to SPI queues
Programmable transfer attributes on a per-frame basis:
— Parameterized number of transfer attribute registers (from two to eight)
— Serial clock with programmable polarity and phase
— Various programmable delays:
– PCS to SCK delay
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