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| 型号： | TRK-MPC5634M |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 29/122页 |
| 文件大小： | 0K |
| 描述： | TRAK 5634M 144PN R2.1 |
| 设计资源： | TRK-MPC5634M Schematic |
| 标准包装： | 1 |
| 系列： | MPC56xx |
| 类型： | MCU |
| 适用于相关产品： | MPC5634M |
| 所含物品： | 板，线缆，CD，DVD |
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MPC5634M Microcontroller Data Sheet, Rev. 9
Overview
Freescale Semiconductor
14
2.2.7
SIU
The MPC5634MSIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO),
internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot
configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block
provides uniform and discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring
of internal and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z335 CPU
core is via the crossbar switch. The SIU provides the following features:
System configuration
— MCU reset configuration via external pins
— Pad configuration control for each pad
— Pad configuration control for virtual I/O via DSPI serialization
System reset monitoring and generation
— Power-on reset support
— Reset status register provides last reset source to software
— Glitch detection on reset input
— Software controlled reset assertion
External interrupt
— 11 interrupt requests
— Rising or falling edge event detection
— Programmable digital filter for glitch rejection
— Critical Interrupt request
— Non-Maskable Interrupt request
GPIO
— GPIO function on 80 I/O pins
— Virtual GPIO on 64 I/O pins via DSPI serialization (requires external deserialization device)
— Dedicated input and output registers for setting each GPIO and Virtual GPIO pin
Internal multiplexing
— Allows serial and parallel chaining of DSPIs
— Allows flexible selection of eQADC trigger inputs
— Allows selection of interrupt requests between external pins and DSPI
2.2.8
ECSM
The error correction status module provides status information regarding platform memory errors reported by error-correcting
codes.
2.2.9
Flash
Devices in the MPC5634M family provide up to 1.5 MB of programmable, non-volatile, flash memory. The non-volatile
memory (NVM) can be used for instruction and/or data storage. The flash module includes a Fetch Accelerator, that optimizes
the performance of the flash array to match the CPU architecture and provides single cycle random access to the flash @
80 MHz. The flash module interfaces the system bus to a dedicated flash memory array controller. For CPU ‘loads’, DMA
transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface
to flash memory. The module contains a four-entry, 128-bit prefetch buffer and a prefetch controller which prefetches sequential
lines of data from the flash array into the buffer. Prefetch buffer hits allow no-wait responses. Normal flash array accesses are
registered and are forwarded to the system bus on the following cycle, incurring three wait-states. Prefetch operations may be
automatically controlled, and are restricted to instruction fetch.
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