参数资料
型号: TRK-MPC5634M
厂商: Freescale Semiconductor
文件页数: 122/122页
文件大小: 0K
描述: TRAK 5634M 144PN R2.1
设计资源: TRK-MPC5634M Schematic
标准包装: 1
系列: MPC56xx
类型: MCU
适用于相关产品: MPC5634M
所含物品: 板,线缆,CD,DVD
Electrical characteristics
MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
99
10
tHI
CC
Data Hold Time for Inputs
D Master (MTFE = 0)
–4
–4
–4
ns
D Slave
7—7—7—
D Master (MTFE = 1,
CPHA = 0)7
45
25
21
D Master (MTFE = 1,
CPHA = 1)
–4
–4
–4
11
tSUO
CC
Data Valid (after SCK edge)
D Master (MTFE = 0)
—6—6—6
ns
D Slave
—25—25
—25
D Master (MTFE = 1,
CPHA=0)
—45—25
—21
D
Master (MTFE = 1,
CPHA=1)
—6—6—6
12
tHO
CC
Data Hold Time for Outputs
D Master (MTFE = 0)
–5
–5
–5
ns
D Slave
5.5
5.5
5.5
D Master (MTFE = 1,
CPHA = 0)
8—4—3—
D Master (MTFE = 1,
CPHA = 1)
–5
–5
–5
1 All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad
types of S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0–5.25
V, TA = TL to TH, and CL = 50 pF with SRC = 0b11.
2 Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency
modulation (FM). 42 MHz parts allow for 40 MHz system clock + 2% FM; 62 MHz parts allow for a 60 MHz system
clock + 2% FM, and 82 MHz parts allow for 80 MHz system clock + 2% FM.
3 The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are
calculated based on two MPC5634M devices communicating over a DSPI link.
4 The actual minimum SCK cycle time is limited by pad performance.
5 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
6 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
7 This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
Table 40. DSPI timing1,2 (continued)
#
Symbol
C
Characteristic
40 MHz
60 MHz
80 MHz
Unit
Min.
Max.
Min.
Max.
Min.
Max.
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