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参数资料
| 型号： | TSPC603RMAB/Q6LC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 |
| 封装： | CERQUAD-240 |
| 文件页数： | 1/40页 |
| 文件大小： | 670K |
| 代理商： | TSPC603RMAB/Q6LC |
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Description
The PID7t-603e implementation of PowerPC603e (after named 603r) is a low-power implementa-
tion of reduced instruction set computer (RISC) microprocessors PowerPC
family. The 603r is
pin-to-pin compatible with PowerPC 603E and 603P in Cerquad package. The 603r implements
32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of
32 and 64 bits.
The 603r is a low-power design and provides four software controllable power-saving modes.
The 603r is a superscalar processor capable of issuing and retiring as many as three instructions
per clock. Instructions can execute out of order for increased performance ; however, the 603r
makes completion appear sequential. The 603r integrates five execution units and is able to exe-
cute five instructions in parallel.
Features
H 5.6 SPECint95, 4.0 SPECfp95 @ 200 MHz (estimated)
H Superscalar (3 instructions per clock peak).
H Dual 16KB caches.
H Selectable bus clock.
H 32-bit compatibility PowerPC implementation.
H On chip debug support.
H PD typical = 2.5 Watts (200 MHz), full operating conditions.
H Nap, doze and sleep modes for power savings.
Screening / Quality /Packaging
This product is manufactured in full
compliance with:
H MIL-STD-883 class Q (TBC) or
According to TCS standards
H Full military temperature range
(Tc = -55°C, Tc= +125°C)
Industrial
temperature
range
(Tc = -40°C, Tc= +110°C)
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier
Cavity up
CERQUAD 240
The 603r provides independent on-chip, 16-Kbyte, four-way set-associative, physically
addressed caches for instructions and data and on-chip instruction and data memory manage-
ment units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction
translation lookaside buffers that provide support for demand-paged virtual memory address
translation and variable-sized block translation.
The 603r has a selectable 32 or 64-bit data bus and a 32-bit address bus. The 603r interface pro-
tocol allows multiple masters to complete for system resources through a central external arbiter.
The 603r supports single-beat and burst data transfers for memory accesses, and supports
memory-mapped I/O.
The 603r uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface
compatibility with TTL devices.
The 603r integrates in system testability and debugging features through JTAG boundary-scan
capability.
TSPC603r
in CERQUAD and
MQUAD Packages
PowerPC 603eTM RISC
MICROPROCESSOR
Family PID7t-603e
Specification
Target Specification
H Commercial temperature range
(Tc = 0°C, Tc= +70°C)
H Internal // I/O Power Supply
2.5
± 5 % // 3.3 V ± 5 %
H 240 pin Cerquad or 240 pin
MQUAD packages
MQUAD 240
Y suffix
MQUAD 240
Metal Quad Flat Pack
Cavity up
August 2000
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